soc/amd/cezanne: add empty ramstage FCH support

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 70df778aff..fd930896a7 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -2,6 +2,7 @@
 
 #include <device/device.h>
 #include <fsp/api.h>
+#include <soc/southbridge.h>
 #include <types.h>
 #include "chip.h"
 
@@ -12,10 +13,13 @@ static void enable_dev(struct device *dev)
 static void soc_init(void *chip_info)
 {
 	fsp_silicon_init(false); /* no S3 support yet */
+
+	fch_init(chip_info);
 }
 
 static void soc_final(void *chip_info)
 {
+	fch_final(chip_info);
 }
 
 struct chip_operations soc_amd_cezanne_ops = {