coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-07-12	soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared	Raul E Rangel
2021-06-16	soc/amd/cezanne/acpi/mmio: use AOAC offset defines	Felix Held
2021-05-09	soc/amd/cezanne: Generate PCI routing table	Raul E Rangel
2021-05-08	soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call	Felix Held
2021-04-21	soc/amd/{cezanne,common}/acpi: Add _OSC method	Raul E Rangel
2021-04-20	soc/amd/{common,cezanne}: Add uPEP device	Raul E Rangel
2021-03-30	soc/amd/cezanne: Comment the AOAC register access	Karthikeyan Ramasubramanian
2021-03-13	soc/amd/cezanne/acpi/soc.asl: Include sleepstates.asl	Raul E Rangel
2021-03-13	soc/amd/cezanne: Move globalnvs.asl to the correct location	Mathew King
2021-02-25	soc/amd/cezanne/acpi: Add globalnvs.asl	Raul E Rangel
2021-02-25	soc/amd/cezanne/acpi/pci0.asl: Add LPC device	Raul E Rangel
2021-02-22	soc/amd/cezanne/acpi: Add pci0.asl	Raul E Rangel
2021-02-22	soc/amd/cezanne/acpi/soc.asl: Add platform.asl	Raul E Rangel
2021-02-22	soc/amd/cezanne/acpi: Add MMIO devices	Raul E Rangel
2021-02-13	soc/amd/cezanne/acpi: Add plain soc.asl	Raul E Rangel