| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-09-14 | acpi/soc: Conditionally include dptc.asl | Tim Van Patten |
| 2022-09-12 | soc/amd: Refactor DPTC Tablet Mode | Tim Van Patten |
| 2021-12-18 | soc/amd/cezanne/acpi: Add support for RTC workaround | Raul E Rangel |
| 2021-05-09 | soc/amd/cezanne: Generate PCI routing table | Raul E Rangel |
| 2021-05-08 | soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call | Felix Held |
| 2021-04-21 | soc/amd/{cezanne,common}/acpi: Add _OSC method | Raul E Rangel |
| 2021-04-20 | soc/amd/{common,cezanne}: Add uPEP device | Raul E Rangel |
| 2021-03-13 | soc/amd/cezanne/acpi/soc.asl: Include sleepstates.asl | Raul E Rangel |
| 2021-03-13 | soc/amd/cezanne: Move globalnvs.asl to the correct location | Mathew King |
| 2021-02-25 | soc/amd/cezanne/acpi: Add globalnvs.asl | Raul E Rangel |
| 2021-02-22 | soc/amd/cezanne/acpi: Add pci0.asl | Raul E Rangel |
| 2021-02-22 | soc/amd/cezanne/acpi/soc.asl: Add platform.asl | Raul E Rangel |
| 2021-02-22 | soc/amd/cezanne/acpi: Add MMIO devices | Raul E Rangel |
| 2021-02-13 | soc/amd/cezanne/acpi: Add plain soc.asl | Raul E Rangel |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |