coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-22	soc/amd/cezanne/acpi: Add pci0.asl	Raul E Rangel
	This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22	soc/amd/cezanne/acpi/soc.asl: Add platform.asl	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22	soc/amd/cezanne/acpi: Add MMIO devices	Raul E Rangel
	The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13	soc/amd/cezanne/acpi: Add plain soc.asl	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>