| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-22 | soc/amd/cezanne/acpi: Add pci0.asl | Raul E Rangel |
| 2021-02-22 | soc/amd/cezanne/acpi/soc.asl: Add platform.asl | Raul E Rangel |
| 2021-02-22 | soc/amd/cezanne/acpi: Add MMIO devices | Raul E Rangel |
| 2021-02-13 | soc/amd/cezanne/acpi: Add plain soc.asl | Raul E Rangel |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |