| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-12-02 | security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS | Michał Żygowski |
| 2021-11-27 | security/intel/txt: Implement GETSEC PARAMETER dumping | Michał Żygowski |
| 2020-11-04 | haswell: Add Intel TXT support in romstage | Angel Pons |
| 2020-10-22 | sec/intel/txt: Only run LockConfig for LT-SX | Angel Pons |
| 2020-10-12 | security/intel/txt: Add and use DPR register layout | Angel Pons |
| 2020-10-12 | security/intel/txt: Clean up includes | Angel Pons |
| 2020-09-21 | src/security: Drop unneeded empty lines | Elyes HAOUAS |
| 2020-08-30 | security/intel/txt: Add missing definitions | Angel Pons |
| 2020-07-31 | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |