| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-07 | cpu/x86: Drop !CPU_INFO_V2 code | Arthur Heymans |
| 2021-12-06 | x86_64 assembly: Don't touch %gs | Patrick Rudolph |
| 2021-12-06 | security/intel: Use defines for segment registers | Patrick Rudolph |
| 2020-10-22 | sec/intel/txt: Split MTRR setup ASM code into a macro | Angel Pons |
| 2020-10-17 | security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] | Angel Pons |
| 2020-10-15 | sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPE | Arthur Heymans |
| 2020-08-07 | security/intel/txt: Fix variable MTRR handling | Angel Pons |
| 2020-07-31 | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |