| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-11-04 | haswell: Add Intel TXT support in romstage | Angel Pons |
| 2020-10-22 | sec/intel/txt: Extract BIOS ACM loading into a function | Angel Pons |
| 2020-10-22 | sec/intel/txt/common.c: Only log ACM error on failure | Angel Pons |
| 2020-10-17 | sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM | Angel Pons |
| 2020-10-12 | security/intel/txt: Clean up includes | Angel Pons |
| 2020-08-07 | security/intel/txt: Allow using CF9 reset, too | Angel Pons |
| 2020-08-06 | security/intel/txt: Avoid shifting by a negative value | John Zhao |
| 2020-07-31 | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |