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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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other fixes for gx2 ram init.
support for sharplfg00l04 -- not working yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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removed some messages
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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still get garbage reading smbus.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is just a skeleton, basically, and will most likely not even
compile yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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48
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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store every HT device unit id base and pass those info to acpi
https://openbios.org/roundup/linuxbios/issue46
Note: This version drops the two scripts a and c and creates the dsdt on
the fly from Config.lb using makerule
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a. apic id liftting to way that kernel like and let bsp
to stay with 0
b. hw memhole: solve if hole_startk == some node
basek
This, together with the previous one will break most of
the tree, but Yinghai Lu is really good
at fixing things, so...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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https://openbios.org/roundup/linuxbios/issue24
- fix up for via epia-m
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This was missed in the checkin of raminit.c changes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- In addition:
Kept K8_HT_FREQ_1G_SUPPORT
to support older boards.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- In addition:
modified apic_id lifting to always lift all CPUs. This may cause problems with older kernels.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* Added code to support remap window for 3 - 4 GB systems
* Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html).
* Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted.
* Disabled subsystem (vendor) ID configuration
* #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html)
* Added optional run-time checking of dual-channel compatibility of installed DIMMs
* Move JEDEC SPD and SDRAM definitions into reusable #include files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Special version for HDAMA rev G with 33Mhz test and reboot out.
- Support for CPU rev E, dual core, memory hoisting,
- corrected an SST flashing problem. Kernel bug work around (NUMA)
- added a Kernel bug work around for assigning CPU's to memory.
r2@gog: svnadmin | 2005-08-03 08:47:54 -0600
Create local LNXI branch
r1110@gog: jschildt | 2005-08-09 10:35:51 -0600
- Merge from Tom Zimmerman's additions to the hdama code for dual core
and 33Mhz fix.
r1111@gog: jschildt | 2005-08-09 11:07:11 -0600
Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
r1112@gog: jschildt | 2005-08-09 15:09:32 -0600
- temporarily removing hdama tag to update to public repository. Will
reset tag after update.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
More Via EPIA
more via epia stuff, including the trival but fatal bug in auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
USE_DCACHE_RAM instead of CONFIG_DCACHE_RAM in raminit.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
x96emu update from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
Nvidia Ck804 support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Hamish Guthrie <hamish@prodigi.ch>
Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Hamish Guthrie <hamish@prodigi.ch>
Added AMD GX1 northbridge and cs5530 Southbridge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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More correct resource allocation for legacy VGA on K8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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correct but it works anyway.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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fixes to emulator.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- optimize_link_read_pointers compiles now on the solo so don't disable it.
- Start sorting out the confusion between and object and an initobject on the ppc ports
- Major bugfix release of romcc to support to remove preprocessor deficiencies.
The line and column numbers are computed are now correct. But watch out
the error messages sometimes report the location of the next token so things
are still a little skewed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.
We're almost as far along as we were before the Change :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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complex expression.
crt0.S.lb: Modified so that it is safe to include console.inc
console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c: Remove work around for older versions of romcc
pci_ids.h: More ids.
malloc.c: We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
- Talk about nodes not cpus (In preparation for dual cores)
- Remove clear_temp_row (as it is no longer needed)
- Demoted the failure messages to spew.
- Modified to gracefully handle failure (It should work now if cpus are removed)
- Handle the non-SMP case in verify_mp_capabilities
- Add clear_dead_routes which replaces clear_temp_row and does more
- Reorganize setup_coherent_ht_domain to cleanly handle failure.
- incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop. It's more maintainable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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