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authorLi-Ta Lo <ollie@lanl.gov>2006-02-28 15:39:25 +0000
committerLi-Ta Lo <ollie@lanl.gov>2006-02-28 15:39:25 +0000
commitbab9446dfd715255d7c8dbefa11a214ffc354cab (patch)
tree224e9ec0007e7d3ca2e677742629642acca1c6fb /src/northbridge
parenta51e6f1e560a1dc40ec0c9522733d5f8422f041f (diff)
semi working with random 1 bit error
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/gx2/raminit.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 1b2ad6a6b9..2ad46b6170 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -48,15 +48,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x2000201d, msr);
print_debug("sdram_enable step 3\r\n");
- /* 4. set and clear REF_TST 16 times, more shouldn't hurt */
- for (i = 0; i < 19; i++) {
- msr = rdmsr(0x20000018);
- msr.lo |= (0x01 << 3);
- wrmsr(0x20000018, msr);
- msr.lo &= !(0x01 << 3);
- wrmsr(0x20000018, msr);
- }
- print_debug("sdram_enable step 4\r\n");
/* 5. set refresh interval */
msr = rdmsr(0x20000018);
@@ -68,7 +59,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= !(0x03 << 6);
wrmsr(0x20000018, msr);
-
/* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
msr.lo |= ((0x01 << 28) | 0x01);
@@ -96,14 +86,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
print_debug("sdram_enable step 10\r\n");
+ /* 4. set and clear REF_TST 16 times, more shouldn't hurt */
+ for (i = 0; i < 19; i++) {
+ msr = rdmsr(0x20000018);
+ msr.lo |= (0x01 << 3);
+ wrmsr(0x20000018, msr);
+ msr.lo &= !(0x01 << 3);
+ wrmsr(0x20000018, msr);
+ }
+ print_debug("sdram_enable step 4\r\n");
+
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
outb(0xaa, 0x80);
/* load RDSYNC */
- msr = rdmsr(0x2000001a);
+ msr = rdmsr(0x2000001f);
msr.hi = 0x000ff310;
- wrmsr(0x20000018, msr);
+ wrmsr(0x2000001f, msr);
print_debug("sdram_enable step 10\r\n");
/* DRAM working now?? */