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2021-04-02nb/intel/pineview: Correct COMP register writeAngel Pons
Reference code does an and-or operation with zero as or-value, reading and writing to the same address. The accessed register is 32-bit, and reference code programs bits 22, 21, 20, 16 to zero. However, coreboot code reads the value from bits 7..0 instead. Correct this. Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/pineview/raminit.c: Correct clkset1 programmingAngel Pons
Reference code does a 32-bit write, and the values don't fit in 16 bits. Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/pineview: Correct HICLKGTCTL writeAngel Pons
Reference code uses the `0x06` as an or-mask, which makes more sense. Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/pineview: Drop MCHBAR macro from DMIBAR accessAngel Pons
While the macro value is the same, the DMIBAR register is not HTBONUS1. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/ironlake/quickpath.c: Correct one valueAngel Pons
Commit 56823f53dc6de5a804f7c88b9f24847133ddc876 (nb/intel/ironlake: Rewrite early QPI init) rewrote this part, but the or-value is missing one zero. Correct this magic value to align with MRC binaries. Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/ironlake: Drop copy-pasted finalisation stepsAngel Pons
This was copied from Sandy Bridge and does not apply to Ironlake. These offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake). Some of these writes would have collided with `DEFAULT_HECIBAR` if the PCI resource had been reported as fixed. Remove the copy-pasted code. Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`Angel Pons
While 64-bit writes seem to work properly, there could be unknown side-effects in some cases, e.g. when running in long mode. Since reference code uses two 32-bit writes, follow suit. Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25nb/intel/haswell: Move USB config API into Lynx PointAngel Pons
Both EHCI and xHCI USB controllers are inside the PCH (southbridge). Now that mainboard USB configuration no longer depends on pei_data.h definitions, the API declarations can be placed in southbridge code. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-25nb/intel/haswell: Decouple mainboard USB config from MRCAngel Pons
With this change, only raminit.c uses pei_data.h definitions. With MRC cornered, making it optional is just a matter of writing a replacement. USB config definitions will be moved to Lynx Point code in a follow-up. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-23nb/intel/haswell: Limit mainboard USB config array lengthsAngel Pons
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit the array lengths accordingly to cause build errors on invalid configs. Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons
It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23nb/intel/haswell: Confine `pei_data` uses to raminit.cAngel Pons
Reorganize romstage.c to resemble sandybridge, and move everything that needs `pei_data` into raminit.c function `perform_raminit`. Barring USB settings, coreboot code no longer depends on pei_data.h definitions. It still depends on MRC, though. For now. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-15sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10nb/intel/haswell: Finalize northbridge in ramstageAngel Pons
There's no need to finalize the northbridge in SMM. This also makes unification with Broadwell easier. Tested on Asrock B85M Pro4, still boots and registers get locked. Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10nb/intel/haswell/pcie.c: Add missing pre-ASPM initAngel Pons
Add devicetree configuration parameters for mainboard-specific settings, and provide reasonable defaults, which should usually be good enough. This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014). Tested on Asrock B85M Pro4, registers now have the expected values. Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47223 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-07nb/intel/haswell: Indent PCI ops with tabsAngel Pons
Change-Id: Ia338ce1a36aa0a14017201c1fc16f84915f55c07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons
Compute timings first, then display them. Drop unneeded comments, too. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak
DPR register's size field is given in whole MiB, so correct where it is used to ensure the correct size multiple (KiB vs. MiB) is used with it. Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling") Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflowAngel Pons
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide. Clamp any values that would overflow this field. Bits in TC_DTP already get set when the tXP and/or tXPDLL values are large. Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27nb/intel/ironlake: Avoid casting pointers to structsAngel Pons
Instead, convert the struct to a union and pass in a pointer to it. Tested on out-of-tree HP ProBook 6550b, still boots. Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27nb/intel/ironlake: Handle broken ME firmwareAngel Pons
This allows booting without ME firmware, even though the 30-minute auto-shutdown still happens. Without this patch, an HP ProBook 6550b cannot get past the `setup_heci_uma` function call. Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-24nb/intel/ironlake: Rewrite early QPI initAngel Pons
Rewrite early QPI initialisation to account for variables in the register values. Trace replays did not capture these relationships. Tested on out-of-tree HP 630, still boots. Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/haswell/northbridge.c: Correct DPR handlingAngel Pons
DPR size is in MiB, but the range boundaries are expressed in KiB. In addition, DPR and TSEG use the same attributes, so unify both regions. Also improve a comment about DPR, since `is special` is uninformative. Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Correct even more replay issuesAngel Pons
The per-lane registers need to be modified in some cases. Also, MRC does not have any delay after the loop, so remove it. Tested on out-of-tree HP 630, still boots. Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Relocate early QuickPath initAngel Pons
Given that the PCI devices/registers being accessed are about QuickPath, this code must be part of QuickPath init. Move it with the other code. Tested on out-of-tree HP 630, still boots. Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Deduplicate programming 274/265 valuesAngel Pons
Transform the existing functions so that their functionality does not overlap. Also, deduplicate printing these values in debug builds. Tested on out-of-tree HP 630, still boots. Change-Id: I3f50dcf56284c9648b116bc5aacc0adf2d863b5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49583 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Split out some QuickPath init codeAngel Pons
The platform performs a CPU-only reset after initializing QPI (QuickPath Interconnect) and before actually performing raminit. The state is saved in the sticky scratchpad register at MCHBAR + 0x2ca8. Relocate some QuickPath init to a separate file. All moved functions are only used within QPI init code, and had to be relocated in one commit. Tested on out-of-tree HP 630, still boots. Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Remove unnecessary declarationAngel Pons
Change-Id: I14c5671dfc611209e28f25f38b4e82d11aef88ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49580 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Fix more replay issuesAngel Pons
Introduce the `get_bits_420` helper to avoid doing the same thing in three different ways, and also correct a related register write. Tested on out-of-tree HP 630, still boots. Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Fix some replay issuesAngel Pons
Dummy reads followed by writes are actually read-modify-write operations in disassembled binaries. Handling of the scratchpad register 0x2ca8 is still nonsense, but that should be taken care of in a separate commit. Tested on out-of-tree HP 630, still boots. Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/ironlake: Correct `set_4cf`Angel Pons
We only need to toggle one bit at a time. Introduce `rmw_500` to simplify the code. The rank population doesn't seem to matter. Tested on out-of-tree HP 630, still boots. Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24device/device.c: Rename .disable to .vga_disableArthur Heymans
This makes it clear what this function pointer is used for. Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/haswell/pcie.c: remove disable NOPArthur Heymans
The .disable function pointer is only referenced inside set_vga_bridge_bits() and is used to unset VGA decoding on the internal GFX device. Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24nb/intel/sandybridge/pcie.c: remove disable NOPArthur Heymans
The .disable function pointer is only referenced inside set_vga_bridge_bits() and is used to unset VGA decoding on the internal GFX device. Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23nb/intel/ironlake: Drop redundant clear of SLP_TYPKyösti Mälkki
Bits are already cleared in southbridge_detect_s3_resume(). Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23nb/intel/x4x: Use a variable for s3resumeKyösti Mälkki
This helps towards unified chipset_power_state. Change-Id: I8f152dc9f1e0f26e4777489913e9fb2c9cd3dac0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23nb/intel/x4x,sandybridge: Move INITRAM timestampsKyösti Mälkki
Let's not have CBMEM hooks in between the different INITRAM timestamps. Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23nb/intel/x4x,sandybridge: Move romstage_handoff_init() callKyösti Mälkki
Change-Id: I6356bb7ea904ca860cbedd46515924505d515791 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23nb/intel/haswell: Use cbmem_recovery()Kyösti Mälkki
For consistency with other nb/intel rename variable from wake_from_s3 to s3resume. Change-Id: If94509c4640f34f2783137ae1f94339e6e6cf971 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22nb/intel/sandybridge: Remove stale FIXME about ECC supportAngel Pons
Change-Id: Id0c45ff1ee4a2dc4c0f9a82f6a311f7acac156fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22nb/intel/ironlake: Do not call `collect_system_info` twiceAngel Pons
Move wait for TXT and early ME init out of `collect_system_info`, and then drop the first call to it. Also drop a useless register read. Tested on out-of-tree HP 630, still boots. Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/pineview: Drop unused `GPIO32` macroAngel Pons
It's not used, and GPIO registers are on the southbridge. Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400Angel Pons
The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/sandybridge: Clean up `dram_freq` functionAngel Pons
The thing that this function initializes is the MPLL (Memory PLL). So, call it by its name. Also add a missing newline in a printk, and update a comment on the callsite of this function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-18nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG writeAngel Pons
This write was copied from Sandy Bridge. Neither Haswell reference code nor Broadwell perform this write. Therefore, it seems safe to remove it. Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb/intel/i945: Use UPMC4 macroElyes HAOUAS
Change-Id: Id3fb39edb0f14d48b9ea84b882fc46790fc37524 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50632 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb/intel: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I801be1ca8da4b1641941d5571d2aa298470f407b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50578 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb/intel: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Ica0354fdfe6861551689e3baef94d364d9ded16d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16nb/intel/sandybridge: Fix description of auto-precharge bitAngel Pons
This bit is primarily used to issue RDA commands. There doesn't seem to be any limitation regarding the number of address bits. Change-Id: I2804f67319c9bc736f9086af408853056aabedd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START. Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki
Communicate the RAMOOPS section via ChromeOS GNVS. Change-Id: I75170e6e34c20db88efa268080d2c38916b31f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16nb/i945/raminit.c: Don't hard code 'bool integrated_graphics'Elyes HAOUAS
Change-Id: I735fa6413128cb9c17d99dfe9ffc3ee93ede51ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/nb: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I55aa05f72e06b509c85f0754320c389de7e75f8d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50525 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15nb/intel/sandybridge: Correct description of QCLKAngel Pons
QCLK means "quadrature clock", and is equivalent to one half of a full clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid. Change-Id: I7089fc32381addc280a71761a377075f107b5c62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12nb/intel/haswell/pei_data.h: Define `SPD_LEN`Angel Pons
Change-Id: I34561372bcdd00b1b3e4dcd6be89fa47d2af9b42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50541 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12nb/intel/haswell: Drop unused function declarationAngel Pons
Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50540 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12haswell: Drop `mainboard_fill_pei_data`Angel Pons
Use global variables to provide mainboard USB settings, and have the northbridge code copy it into the `pei_data` struct. For now. To minimize diffstat noise, this patch does not reindent the now-global mainboard USB configuration arrays. This is cleaned up in a follow-up. Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`Angel Pons
64-bit builds need this, as the Kconfig values fit in a 32-bit integer. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-11sb/intel/ibexpeak: Drop Global NVS supportAngel Pons
Was copy-pasted from bd82x6x and no mainboard actually needs it. The few globals moved outside the GNVS will be removed, relocated or replaced with acpigen later. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src: Remove unused <cpu/intel/model_206ax/model_206ax.h>Elyes HAOUAS
Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in commentElyes HAOUAS
Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10nb/intel/i945: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/x4x: Correct DDR3 turnaround tableAngel Pons
Comparing against MRC, looks like the values for TA3 and TA4 are backwards. All of them. Thus, correct the tables accordingly. Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works. Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4 Tested-by: Michael Büchler <michael.buechler@posteo.net> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Büchler <michael.buechler@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/x4x: Constify write leveling arraysAngel Pons
Change-Id: I3be3952aaba1fe2da5490b071b4e3609773e84a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Update write leveling commentAngel Pons
Fix a typo and do some style improvements. Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-07nb/intel/pineview: Rewrite hex values in lowercaseAngel Pons
Most hex values are already lowercase. For consistency reasons, rewrite uppercase hex values in lowercase. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I185b448ca7822fa89c57efe788e05b582b259c37 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50356 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/pineview: Delete rude and useless commentAngel Pons
Change-Id: I5bcadf04b5d5b9dad3523bce98942f2792be905f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50357 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/pineview: Clean up FIXMEs in raminitNico Huber
Using MCHBAR32_AND_OR() in these two cases changes the order of additions slightly. Originally, the MCHBAR offset and the base register offset (0x5a4/0x5b4) were added first. Due to the added parentheses in the register macros, now the complete register offset is calculated first and then added to MCHBAR. Associativity tells us that this doesn't change the result. Changes in the resulting binary were verified manually on the object file. Change-Id: Id10882225c8e82b02583aa73e73d661c25abdef9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50355 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/x4x: Constify DDR2 ODT tableAngel Pons
Change-Id: Id5b5dc584ab93620ae58cf43fe0d47015d512f82 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Clean up RCOMP cosmeticsAngel Pons
Clean up cosmetics after refactoring the code. Reflow long lines and align values in the tables, and also remove a now-unnecessary scope. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Drop unused first array indexAngel Pons
The first RCOMP group (data) is programmed differently, and has its own tables. Remove the unused first index from the other tables, and adjust the loop bound accordingly. Cosmetics are cleaned up in a follow-up. Tested on Asus P5QL PRO (DDR2), still boots. Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Unroll programming RCOMP data groupAngel Pons
The RCOMP data group is special and is programmed differently. Prepare to simplify the code by programming it outside of the loop. Subsequent commits will simplify the logic even further, then clean up cosmetics. The special DDR3 case in the loop overwrites the command group strength multiplier value. It doesn't need to be programmed for each RCOMP group. Add a comment to justify not programming this register while programming the settings for the RCOMP data group. Tested on Asus P5QL PRO (DDR2), still boots. Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Report if running in async modeAngel Pons
Change-Id: I84d5457173598e8ff41dfb048a6858b41c5692ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Factor out setting Tx DLL tap and PIAngel Pons
These settings can be programmed with a single register write. Factor the writes out into a single function to avoid some redundancy. Tested on Asus P5QL PRO, still boots. Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Correct ctrlset{2,3} register maskAngel Pons
MRC uses an incorrect mask when programming this register, but the reset default value is zero and it is only programmed once. As it makes no difference, we can safely use the correct mask. Document this difference in a comment to indicate the deviation from MRC behavior is intentional. The default value for this register was dumped from Asus P5QL PRO. Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Clean up cosmetics of raminit tablesAngel Pons
Consistently use commas after the last element of arrays, and also align columns of values and comments. Remove `MHz` units from DDR speed values to avoid confusion, as the memory's actual clock speed is half of these. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/x4x: Drop commented-out statementAngel Pons
Time has proven this statement to be unnecessary. Uncommenting it would not have any effect on the existing code, thus remove it completely. Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessorsAngel Pons
These accessors can be reused for several other northbridges. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/ironlake: Avoid pointer arithmeticsAngel Pons
Drop casts to prevent pointer arithmetic and for consistency with other platforms. These macros will be factored out in a subsequent commit. Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49747 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07nb/intel/pineview: Guard {MCH,DMI,EP}BAR macrosAngel Pons
Guarding the MCHBAR macro breaks reproducibility, but should not have any functional impact. Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49746 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Define `RCBA_LENGTH` in Kconfig and use itAngel Pons
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAYKyösti Mälkki
It was commented that the need for the delay was mainly related to external displays and only with VBIOS execution. Move the delay such that it is done only when we actually need to execute the VBIOS aka option rom. A delay is currently only defined for librem/purism_bdw in its Kconfig. As the description of the issue sounds like it would equally happen on other platforms when VBIOS is involved, promote the Kconfig visible option to global scope. Change-Id: I4503158576f35057373f003586bbf76af4d59b3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`Angel Pons
This partially reverts: - Commit 77d3b655ed - Commit 487c1a24f5 - Commit 875c21f491 - Commit c4d1b47ad9 - Commit b96c358751 - Commit 9cbf26d18e It is intentional to use <device/pci_ops.h> whenever one needs to use PCI config access. The bootblock.c files needing I/O config do not need to be an exception to this. Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
Also replace 'reg' with 'reg32'. Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 15:44:50 +0000