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path: root/src/northbridge
AgeCommit message (Expand)Author
2016-04-20AMD CIMX: Drop unused codeKyösti Mälkki
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
2016-04-16northbridge/amd/{lx,gx2}: remove immediate accesses of 0Patrick Georgi
2016-04-13amd/agesa/family12/dimmSpd.c: Indent (tab) fixEdward O'Callaghan
2016-04-11and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignmentTimothy Pearson
2016-04-11nb/amd/amdfam10: Write MCT variables to flash after PCI configurationTimothy Pearson
2016-04-10nb/intel/sandybridge/raminit: always use mrccachePatrick Rudolph
2016-04-08Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"Timothy Pearson
2016-04-08nb/amd/mct_ddr3: Reenable sync flood after ECC initTimothy Pearson
2016-04-08nb/amd/mct_ddr3: Add MCE reporting logicTimothy Pearson
2016-04-08nb/amd/amdfam10: Only flag machine check exception if valid bit is setTimothy Pearson
2016-04-08nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform levelTimothy Pearson
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
2016-04-01nb/amd/mct_ddr3: Fix revision mask for DR processorsTimothy Pearson
2016-03-31nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstageTimothy Pearson
2016-03-31nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEsTimothy Pearson
2016-03-31nb/amd/mct_ddr3: Disable MCE framework during DRAM trainingTimothy Pearson
2016-03-30nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installedTimothy Pearson
2016-03-30northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)Damien Zammit
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
2016-03-28nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()Timothy Pearson
2016-03-26nb/amd/amdmct: Select max_lanes based on ECC presence or absenceDamien Zammit
2016-03-24nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained valuesTimothy Pearson
2016-03-23nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...Timothy Pearson
2016-03-21nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
2016-03-13nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
2016-03-11nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-28northbridge/intel: add missing #include guardsIru Cai
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
2016-02-19nb/amd/amdmct: Add socket specific configuration for FM2Damien Zammit
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
2016-02-09Revert "northbridge/intel/peg: Disable unused ports"Nico Huber
2016-02-05nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15hTimothy Pearson
2016-02-05nb/amd/mct_ddr3: Work around RDIMM training failureTimothy Pearson
2016-02-04northbridge/intel/peg: Disable unused portsPatrick Rudolph
2016-02-04nb/intel/sandybridge/raminit: Fix two dimms per channelPatrick Rudolph
2016-02-02src: Fix various spelling and whitespace issues.Martin Roth
2016-02-01nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resumeTimothy Pearson
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
2016-01-29Revert "northbridge/intel/sandybridge: Fix random raminit failures"Vladimir Serbinenko
2016-01-29nb/amdmct/mct_ddr3: Enable mainboard voltage setTimothy Pearson
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
2016-01-29nb/intel/x4x: Move to early cbmemDamien Zammit
2016-01-29nb/intel/x4x: Cleanup gma.cDamien Zammit
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
2016-01-28via/cx700: Use zeroptr over 0Patrick Georgi
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
2016-01-26nb/intel/pineview: Increase MMCONF decoding to 256 bussesDamien Zammit
2016-01-24nb/amd/mct_ddr3: Properly set MR0 WR valueTimothy Pearson
2016-01-24nb/amd/mct_ddr3: Add additional verbose-level debug statementsTimothy Pearson
2016-01-24nb/amd/mct_ddr3: Update drive strength configurationTimothy Pearson
2016-01-24northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devicesTimothy Pearson
2016-01-24northbridge/amd/amdmct: Add termination and timing values for C32 socketsTimothy Pearson
2016-01-24northbridge/amd/amdfam10: Update DRAM speed limits for C32 socketsTimothy Pearson
2016-01-20nb/intel/pineview: Use macro names for memory base registersDamien Zammit
2016-01-18nb/intel/pineview: Fix decode_pciebar()Damien Zammit
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
2016-01-17intel/sandybridge/raminit: fix ODT settingPatrick Rudolph
2016-01-14nb/intel/gm45: Backport configuration of panel power timingsNico Huber
2016-01-14nb/intel/gm45: Drop unnecessary panel power handlingNico Huber
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
2016-01-13intel/northbridge/sandy: raminit code cleanupPatrick Rudolph
2016-01-13northbridge/intel/x4x: clean up includesMartin Roth
2016-01-12nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` styleNico Huber
2016-01-07Correct some common spelling mistakesMartin Roth
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