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2022-12-12nb/intel/haswell: Introduce option to not use MRC.binAngel Pons
Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow booting coreboot on Haswell mainboards without the need of the closed source MRC.bin. For now, this option does not work at all; the needed magic will be implemented in subsequent commits. Add a config file to make sure the newly-introduced option gets build-tested. Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/pineview: Use read32p()Elyes Haouas
Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/haswell: Use {read,write}32p()Elyes Haouas
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/x4x: Use read32p()Elyes Haouas
Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/e7505: Use read32p()Elyes Haouas
Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/sandybridge: Use read{8,32}p()Elyes Haouas
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/sandybridge: Use write32p()Elyes Haouas
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clockElyes Haouas
Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'Elyes Haouas
'gpu_lvds_use_spread_spectrum_clock'is only used on i945. Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans
Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans
Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-30nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetreeArthur Heymans
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans
This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30nb/intel/e7505: Hook up PCI domain and CPU ops to devicetreeKyösti Mälkki
Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28aopen/dxplplusu: Support SMM_ASEG and SMM_TSEGKyösti Mälkki
Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-25cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans
The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-22src/northbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-17intel/haswell,lynxpoint: Fix out() parameter orderKyösti Mälkki
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-11-17nb/intel/ironlake,sandybridge/gma: Fix out() parameter orderKyösti Mälkki
Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17sb/intel/i82801dx: Improve LPC device early initKyösti Mälkki
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetreeArthur Heymans
Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12nb/intel/ironlake: Work around unused variable warningArthur Heymans
It's not clear whether this variable should actually be used or not so leave it be with a FIXME comment. Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/pineview: Specify supported memory typesElyes Haouas
Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/x4x: Specify supported memory typesElyes Haouas
Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/sandybridge: Specify supported memory typesElyes Haouas
Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/gm45: Specify supported memory typesElyes Haouas
Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04nb/intel/i945: Specify supported memory typeElyes Haouas
Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03nb/intel/gm45: Make polling loops more explicitAngel Pons
Replace `while (...);` with `do {} while (...);` so that it's easier to distinguish polling loops from something else, like function calls. The `{}` can be understood as "nothing", so that the construct is naturally read as "do nothing while (...)". Another reason to prefer this method is that Jenkins does not complain. Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22nb/intel/i945/raminit: Use 'bool' for do_resetElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22nb/intel/i945/raminit: Use 'size_t' for banksize[]Elyes Haouas
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21nb/x4x/dq_dqs.c: Use 'enum cb_err'Elyes Haouas
Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21nb/intel/x4x/raminit.c: Use 'enum cb_err'Elyes Haouas
Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21nb/intel/i945/rcven.c: Use read32p()Elyes Haouas
Tested on unsupported mainboard (945g-m4). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1935308cc50abd651b52d6290d66180905c6a521 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-20nb/intel/i945/i945.h: Drop useless guardElyes Haouas
i945.h file is not used to generate asl files. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20nb/intel/i945: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20intel/i945: Use 'bool' for dual_channel and interleavedElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-12nb/intel/i945/raminit: Include `inttypes.h` for PRIxPTRPaul Menzel
Selecting *Output verbose RAM init debug messages* (`CONFIG_DEBUG_RAM_SETUP=y`) the build fails due to the missing header. CC romstage/northbridge/intel/i945/raminit.o src/northbridge/intel/i945/raminit.c: In function 'ram_read32': src/northbridge/intel/i945/raminit.c:77:39: error: expected ')' before 'PRIxPTR' 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~ src/northbridge/intel/i945/raminit.c:25:52: note: in definition of macro 'PRINTK_DEBUG' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:22:1: note: 'PRIxPTR' is defined in header '<inttypes.h>'; did you forget to '#include <inttypes.h>'? 21 | #include "chip.h" +++ |+#include <inttypes.h> 22 | src/northbridge/intel/i945/raminit.c:25:39: note: to match this '(' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:77:9: note: in expansion of macro 'PRINTK_DEBUG' 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~~~~~~ src/northbridge/intel/i945/raminit.c:77:22: error: spurious trailing '%' in format [-Werror=format=] 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~~~~~~~~~~ src/northbridge/intel/i945/raminit.c:25:52: note: in definition of macro 'PRINTK_DEBUG' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:77:36: note: format string is defined here 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^ Include `inttypes.h` to fix it. Fixes: e8bb6d2b16ac ("Output verbose RAM init debug messages") Change-Id: If3851ec899d4c7ce5fd64542827f9e0eb546d68b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-10nb/intel/i945/raminit.c: Fix formatted printElyes Haouas
Change-Id: I7122988a1c88175a2e72c11bb95bfa434ce48ff2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicate to check if pci device is on n-th busFabio Aiuto
use function to check if pci device is on a particular bus number. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68103 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06nb/intel/i945/memmap.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie5d7d1dd446428d12a2f904545682e8fb9cd82f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06nb/intel/i945/rcven.c: Sort includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06nb/intel/i945/raminit.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I94a81a30950cca6be5ba36a25f8bc6f87c2aad2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-29nb/intel/i945/raminit.c: Use read32p()Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic0361e5d928c24cfe7dc0a8b0385fbe73d906b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62365 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Petr Cvek <petrcvekcz@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26nb/intel/sandybridge: Align TOUUD down to 1 MiB granularityArthur Heymans
This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007 (nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part. Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17nb/intel/sandybridge/raminit_mrc.c: Use semicolon instead of commaElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15d7e2f30b054d14009761006a2f89f45e001118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-14northbridge/intel/i945: Fix GCC optimizing out cache preload jumpPetr Cvek
Clock config setup must be run from cache. Original code used "goto" to prefetch the code required to update the VCO (by jumping after the code and back before). The GCC since at least 12.1.0 and clang since at least 13.0.1 will elimitate these jumps. Use inline assembler to force the original code flow. TEST=Verified assembly code is the same as generated by GCC 12.1.0 and boot tested on Kontron 986LCD-M. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-30nb/intel: Drop local legacy_hole definitionsKyösti Mälkki
These are architectural and followup works will address the VGA MMIO and/or ASEG better. Change-Id: I88e1dca8058661e31ba934b9860751e13a107108 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24nb/intel/gm45/acpi: Fix max PCI bus numberNico Huber
Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives the maximum PCI bus number at runtime. However, IASL complains about the initial 0 in the resource template, which rendered the PB00 definition self-contradictory at build time (maximum was lower than minimum + length - 1). Let's return to the old default values (min: 0, max: 255, length: 256) and adapt max and length at runtime. Also fix some surrounding whites- pace. NB. The issue wasn't detected before merging commit 0cc56a2848 because of broken IASL versions that can't count errors. Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20intel/gma: Use bitwise or instead addition for valid bitPetr Cvek
Page table entries bit 0 is used as "valid". Its value should be set by a bitwise OR and not by an addition. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I14467081c8279af4611007a25aefab606c61a058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-02nb/intel/i440bx: Use PARALLEL_MPArthur Heymans
The ramstage size is decreased by roughly 5K, but the compressed size increased by ~1K. Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59693 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24nb/intel/i945,gm45: Use incrementing index with fixed resourceKyösti Mälkki
Do this for consistency, while followup will remove the index completely. Change-Id: I7b4822c3909801e91627ed2ffe776d65dfab08d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16northbridge/intel/i945: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16src: Remove unused <cf9_reset.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-13nb/intel/snb/raminit_mrc.c: Remove set but unused variableArthur Heymans
Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45: Enable 64bit supportArthur Heymans
This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs Tested on Thinkpad X200: boots fine to the payload Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45/iommu.c: Fix clearing GTTArthur Heymans
This was dead code as it was checking for the wrong bit (bit 11 indicates the use of shadow GTT). It was doing it at the wrong place regardless as no BARs are set up. Move the code clearing GTT into the GMA .init code and do it unconditionally: if the GTT does not match 2M then the cycles are simply not decoded. Tested on thinkpad X200. Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45/dsdt: Fix number of PCI bussesArthur Heymans
Linux complained that the numbers in DSDT (256) don't match with the values in MMCONF (64). Change-Id: I2ccac64934e8d284e68945f86ec46cb2bf896277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45: Allow for PCI BARs above 4GArthur Heymans
Linux needs to know that allocating BARs above 4G is fine so reserve a region in ACPI for that. Tested on thinkpad X200: a PCIe window gets allocated above 4G and Linux does not relocate it. Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-04-27nb/intel/pineview: Use cbfs mcacheArthur Heymans
There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache. Tested on Gigabyte GA-D510UD, still boots and resumes. Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-24northbridge/intel: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I72a0f26b79cf0f61338876cf58d143f7ef3cad3b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-22nb/intel/i945/memmap.c: Fix TOLUD bit field maskPetr Cvek
Register TOLUD is defined as bit field 7:3 (section 5.1.26, page 103, i945GM datasheet), fix the mask accordingly. Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49 Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-20nb/intel/snb: Reduce scope of functionsArthur Heymans
Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-10nb/intel/sandybridge: Restore `mainboard_early_init()` callAngel Pons
Commit 7a874330919a4df9cc5b66058b4340465b7ea041 (mb/google,samsung: Drop init_bootmode_straps()) got rid of the `mainboard_early_init()` function call and weak definition in Sandy Bridge code. However, this function is still used by several Sandy Bridge mainboards, so bring back the dropped call and weak definition. The aforementioned commit did not cause any build-time errors because it did not remove the `mainboard_early_init()` function declaration. Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-09mb/google,samsung: Drop init_bootmode_straps()Kyösti Mälkki
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-28nb/intel/sandybridge/acpi: Support setting PCI bars above 4GArthur Heymans
Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-25nb/intel/gm45/pm.c: Make clang happyArthur Heymans
Clang complains that the terniary '?' operator is executed before the bitwise '|'. This is true and desired in this case. Being explicit about won't hurt however. Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24nb/intel/ironlake: Clean up `jedec_read()` functionAngel Pons
Deduplicate a condition and reflow some lines. Tested on HP ProBook 6550b, still reaches TianoCore payload. Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24nb/intel/ironlake: Fix some quickpath init magicAngel Pons
Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons
Move the remaining HECI-related stuff to southbridge scope, as the HECI hardware is in the southbridge. Note that HECI BAR is now enabled a bit earlier than before, but this shouldn't matter. Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15nb/intel/ironlake/raminit_heci.c: Move to southbridge scopeAngel Pons
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridgeAngel Pons
Remove all northbridge dependencies in the `setup_heci_uma()` function. Update its signature to not pull in raminit internals and drop a dummy read that doesn't have any side-effects (it's probably a leftover from a replay of vendor firmware). This code will be moved into southbridge scope in a follow-up. Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake/raminit_heci.c: Turn into compilation unitAngel Pons
Remove the temporary `raminit_heci.c` include and make it a proper compilation unit. Export the `setup_heci_uma()` function. Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Split out HECI code out of raminitAngel Pons
Move HECI code out of raminit.c into a separate raminit_heci.c file. To preserve reproducibility, use a temporary .c include. This will be gone in a follow-up. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMERKyösti Mälkki
Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-04nb/intel/haswell: Report SMBIOS memory speed in MT/sAngel Pons
The memory speed values in SMBIOS tables are expressed in MT/s, not MHz. Adjust the reported frequency values accordingly. Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61504 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31nb/intel/gm45/raminit.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macrosElyes HAOUAS
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macroElyes HAOUAS
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macrosElyes HAOUAS
Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width' Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 08:38:03 +0000