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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2013-03-15Google Link: Add remaining code to support native graphicsRonald G. Minnich
2013-03-15haswell: Fix BDSM and BGSM indicies in memory mapAaron Durbin
2013-03-15haswell: reserve default SMRAM spaceAaron Durbin
2013-03-15haswell: resource allocationAaron Durbin
2013-03-14haswell: more ULT/LP support and minor tweaksDuncan Laurie
2013-03-14haswell: Add VGA PCI ID mappingsAaron Durbin
2013-03-14haswell: Add ULT device IDsDuncan Laurie
2013-03-14graysreef: update platform informationAaron Durbin
2013-03-14haswell: remove explicit pcie config accessesAaron Durbin
2013-03-14haswell: add PCI id supportAaron Durbin
2013-03-14haswell: Remove logic to send dram init done to MEAaron Durbin
2013-03-14haswell: notes and updates.Aaron Durbin
2013-03-14haswell: align pei_data structure with intel-frameworkAaron Durbin
2013-03-14haswell: use #defines for constants in udelay.cAaron Durbin
2013-03-14haswell: Add LPT LP device IDs to platform reportDuncan Laurie
2013-03-14haswell: Update GPU power management setupDuncan Laurie
2013-03-14haswell: always use MMIO PCI config accessesAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
2013-03-09Add Intel Panther Point USB3 initializationMarc Jones
2013-03-07Intel e7505: provide get_top_of_ramKyösti Mälkki
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
2013-01-14Support for Celeron 1007UStefan Reinauer
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
2012-11-27Drop driver-y from GM45/ICH9/RK9Stefan Reinauer
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-27intel/gm45: new northbridgePatrick Georgi
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
2012-11-17Use new system agent binariesStefan Reinauer
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
2012-11-14pei_data.h: Fix commentMarc Jones
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
2012-11-09Make register/value lists constStefan Reinauer
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
2012-11-07Add missing newline in error messageStefan Reinauer
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-25HAVE_HIGH_TABLES is gonePatrick Georgi
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
2012-08-07Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
2012-08-01Intel Sandybridge and UMA: use mmio_resource()Kyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-30sandybridge: reinitialize usbdebug after MRCSven Schnelle
2012-07-27Intel and GFXUMA: fix MTRR and use uma_resource()Kyösti Mälkki
2012-07-27Intel 82810 and 82830: always room for PCI memoryKyösti Mälkki
2012-07-27Intel i945 and sch: no memory over 4GBKyösti Mälkki
2012-07-26Refactor driver structsPatrick Georgi
2012-07-26CTDP: Only do TDP down/nominal change from TNP0Duncan Laurie
2012-07-26ACPI: Add support for runtime config TDP downDuncan Laurie
2012-07-25ELOG: Add support for a monotonic boot counter in CMOSDuncan Laurie
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
2012-07-24Print PCI ID of PCH during boot upStefan Reinauer
2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
2012-07-24Fix MRC cache update delaysStefan Reinauer
2012-07-24SandyBridge: Add another PCI device ID for northbridgeWalter Murphy
2012-07-24Fixes to enable RC6 on IvyBridgeDuncan Laurie
2012-07-22i945: Disable IGD if plugin VGA is preferredPatrick Georgi
2012-07-20Fix udelay() implementation for i945 romstageNico Huber
2012-07-20Intel SCH northbridge: fix resource indexKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-16i5000: Fix resource allocationSven Schnelle
2012-07-09i5000: reset system if raminit failsSven Schnelle
2012-07-06i5000: Add PCI ids for all i5000 flavoursSven Schnelle
2012-07-06i945: Reset IGD on bootPatrick Georgi
2012-06-20i5000: fix another typoSven Schnelle
2012-06-20i5000: fix typosSven Schnelle
2012-06-18i5000: enforce hard resetSven Schnelle
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
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