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2020-03-26nb/intel/sandybridge: Add print for PLL_REF100_CFGAngel Pons
This field can take eight different values, depending on the maximum supported speed for the memory when using the 100 MHz reference clock. Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-26nb/intel/sandybridge: Rewrite get_FRQAngel Pons
The code is just clamping the frequency index to a valid range. Do it with a helper function. Also, add a CPUID check, as Sandy Bridge will eventually use this code. Change-Id: I4c7aa5f7615c6edb1ab62fb004abb126df9d284b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-25nb/intel/sandybridge: Cache FRQ indexAngel Pons
It does not change once a frequency has been set, so store it somewhere. Since this changes the saved data definition, update MRC_CACHE_VERSION. As SNB will eventually use the same code, only IVB is being refactored. Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-25nb/intel/sandybridge: Rewrite table accessorsAngel Pons
There is no need to call get_FRQ a dozen times with the same parameters. As SNB will eventually use the same code, only IVB is being refactored. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-25drivers/intel/gma/acpi: Add Kconfigs for backlight registersNico Huber
Instead of adding more versions of the `*pch.asl`, unify the existing ones and allow to override the register locations via Kconfig. The current defaults should work for Skylake and some newer platforms. TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2020-03-25nb/intel/sandybridge: Factor out timing tablesAngel Pons
The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables. Move the latter to a common place, and use it for both generations. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work. Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
Note that pei_data.h uses the BSD 3-Clause license: https://opensource.org/licenses/BSD-3-Clause Change-Id: I904b343283239af4fdee583bcbea757f59a0cca7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
Now that we have it, we might as well pass it around. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Void MRC cache if CPUID differsAngel Pons
Native raminit asserts that the DIMMs haven't been replaced before reusing the saved training data. However, it does not check if the CPU is still the same, so it can end up happily reusing data from an Ivy Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code path. This can make the CPU run in unsupported configurations, which may result in an unstable system, or a failure to boot. To prevent that, ensure that the stored CPUID matches the CPUID of the installed CPU. If they differ, print a message and do not use the saved data. As it does not pose a problem for a regular boot, but precludes resuming from S3, use different loglevels depending on the bootpath. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well. Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23nb/intel/sandybridge: Store CPUID in ctrl structAngel Pons
Instead of storing an int with a single bit of information taken from the CPUID, we might as well store the actual CPUID. And since we are changing the definition of the saved data, bump the version number. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: I6ac435fb83900a52890f823e7614055061299e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Add warning to saved structsAngel Pons
When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted. Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Remove unnecessary declarationAngel Pons
Change-Id: If99fd6511fcea474a1398d2b680e0df4bb1a229b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39755 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Do not define tables in a headerAngel Pons
Header files are supposed to not make allocations from .bss. Builds fail if said file is included multiple times. To prevent this from happening, move the definitions to a C file. Also, rename raminit_patterns to raminit_tables. This is because more tables that are not patterns will be added here in subsequent changes. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: If8e3a285ecdc4df9e978ae156be915ced6e1750b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39754 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Reflow raminit tablesAngel Pons
Make them fit in 96 characters, so that Jenkins does not complain. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: I4a763f6050593e9d4db9211bfeedb442724e1ace Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39719 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23nb/intel/sandybridge: Remove oddball `- 1` in tRFCAngel Pons
Fixes a blunder in commit 50db9c99be7e09aafb7cfd353bd0ac9878b76fca (nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings). Tested on Asus P8Z77-V LX2, still boots fine with an i7-2600. Change-Id: I73436b9f7df9f3a065469fb89bcd0cc6183bb774 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-22nb/intel/sandybridge: Drop spurious register writeAngel Pons
It does not make sense to disable an optimization that was not enabled before, especially if that optimization only applies to Ivy Bridge. Tested, still boots and can suspend correctly with: - Asus P8Z77-V LX2 with i5-3330 and Windows 10 - Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-20nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons
Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20nb/intel/sandybridge: Always write to PEGCTLAngel Pons
This register needs to be written to once to lock it down. Do so. Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19nb/intel/sandybridge: Use loops on DMI register groupsAngel Pons
The DMI link consists of four lanes, grouped in two bundles. Therefore, some DMI registers may be organized as "per-lane" or "per-bundle". This can be seen in the DMI initialization sequence as series of equidistant offsets being programmed with the same value. Make this more obvious by factoring out the register groups using loops. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
- Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16nb/intel/i945/raminit: Simplify if conditionPaul Menzel
Use De Morgan’s law to simplify the condition by getting rid of the negations. TEST=With `make BUILD_TIMELESS=1` getac/p470 remains unchanged. Change-Id: I041f2740d6991f9b4e6b8f77988b970c028ca512 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15nb/intel/pineview: Clean up code and commentsAngel Pons
- Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15nb/intel/i945/raminit: Use boolean type for helper variablesPaul Menzel
Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15nb/intel/i945/raminit: Remove space for correct alignmentPaul Menzel
Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-15nb/intel/haswell: Tidy up code and commentsAngel Pons
- Reformat some lines of code - Put names to all used MCHBAR registers - Move MCHBAR registers into a separate file, for future expansion - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) Tested, it does not change the binary of Asrock B85M Pro4. Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11intel/i945: Call fixup_i945_errata() only for mobile versionElyes HAOUAS
Per Mobile Intel ® 945 Express Chipset Family - Specification Update Document Number: 309220-013 (page 15), the power saving optimization Erratum is for Mobile Intel ® 945 Express Chipset family. So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply that function only for I945GM. Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07src/nb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I7dd6dd8e8debe1b6419625fca38670be375ef581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06northbridge: Remove unused include <device/pci.h>Elyes HAOUAS
Change-Id: I942457a820a59428f7ae302262c4891a4c5ef1a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37520 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06nb/intel/haswell/peg: Add PEG driver stubChris Morgan
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded. Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-04nb/intel/nehalem: Use cache.h functionsArthur Heymans
Some local functions need renaming to avoid name collision. Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02nb/intel/sandybridge: Fix VBOOTPatrick Rudolph
The VBOOT code can be compiled but it asserts with: ASSERTION ERROR: file 'src/security/vboot/common.c', line 40 Start VBOOT in bootblock to fix the assertion. Tested on Lenovo X220: The assertion is gone, the platform boots again. Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24src: capitalize 'RAM'Elyes HAOUAS
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-21nb/intel/snb: Add PCI routing table for PEG root portsJames Ye
Previously the PRTs were defined in southbridge code (8014714 southbridge/intel/bd82x6x/acpi: Fix IRQ warnings), but this was lost when southbridge PRTs became autogenerated. Add the proper PRTs for the PCI express for graphics root ports. This (again) fixes warnings issued by Linux for interrupts on secondary functions of devices on the PEG ports, such as the HDMI audio controller on graphics cards. pcieport 0000:00:01.0: can't derive routing for PCI INT B snd_hda_intel 0000:01:00.1: PCI INT B: no GSI Tested with GIGABYTE P67A-UD3R (CB:31363) with Radeon HD 5670. Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-18nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI IDJonathan A. Kollasch
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18nb/intel/sandybridge: use list of northbridge device IDsJonathan A. Kollasch
Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17nb/intel/gm45: Fix typo in console messageElyes HAOUAS
Change-Id: Ia0d7d5ecf376af97ee54ff3ca536160202e43f79 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-17nb/intel/nehalem: Remove unused MRC_CACHE_SIZEElyes HAOUAS
Change-Id: I5d00fb238be6399ea6e9f394d8f899b03b1d44cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-12nb/intel/sandybridge/acpi: Fix MMCONF size computationPatrick Rudolph
Calculate the correct MMCONF size, which was only correct for 256MiB, but not for smaller values. Tested on HP Z220: Fixes "Not using MMCONF" warning in dmesg. Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
2020-02-12nb/intel/sandybridge/acpi: Update PEG codePatrick Rudolph
* Use new ACPI syntax * Return either 0 or 0xf for PCI root port. That will make the device show up in Windows. This might help users and possibly Windows drivers working with PCIe ports. Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-06nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)Chris Morgan
The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board to enable the dGPU. Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01nb/intel/sandybridge: improve indexed register helper macrosFelix Held
Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-29nb/intel/i945: Use boot path macrosPaul Menzel
Change-Id: I932bd0cb97507fa159d1fe3cf2335beb31ca1caf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-27nb/intel/sandybridge/raminit_common.h: add missing stdint.h includeFelix Held
Types from stdint.h are used in that header file without stdint.h being included. Change-Id: I71449dd26162dc8420c206285896ac9a8e4e04d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-27nb/intel/sandybridge: replace NORTHBRIDGE with HOST_BRIDGE defineFelix Held
The two defines are identical, so deduplicate this. Timeless build for lenovo/x230 results in identical binary. Change-Id: I32e0eee88d72eb6f8dc71b0324d62f46079120a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-26intel/i440bx: Resolve long standing raminit TODOsKeith Hui
Drop DRAMT write as it's only rewriting the power on default. PMCR write is required. Update comment on its purpose and move to end of sdram_enable(). Change-Id: I62e8b2531f0f297ffb7db440db89ffa65771b7d5 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-26intel/i440bx: Add timestamp to RAM initKeith Hui
Change-Id: I27b2fcf6fea18e03dddb015eb017acc5db1db540 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-26intel/i440bx: Use smbus_read_byte() for raminit debugKeith Hui
Build broke with CONFIG_DEBUG_RAM_SETUP enabled after commit 3f882faf (intel/i440bx,i82371: Remove wrapper spd_read_byte()). This is the fix. Change-Id: Ib83885fc50c8fab61ced5ff18f22aa4655c5aaab Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
This patch doesn't change the resulting binary of a timeless build. Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
This is to get a uniform format that matches the macros added in the next patch, so that said follow-up patch won't change the output binary. lenovo/x230 still boots with this patch. Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held
LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order of computation, so that the big refactoring doesn't change the output binary of a timeless build. Now this workaround can be dropped. Tested on lenovo/x230: still boots Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15nb/intel/sandybridge: Repurpose HOST_BRIDGE macroAngel Pons
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be replaced with config_of_soc() in a follow-up. Tested with BUILD_TIMELESS=1, resulting binary is identical. Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14intel/nehalem,ibexpeak: Move enable_smbus() callKyösti Mälkki
Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/sandybridge,bd82x6x: Move enable_smbus() callKyösti Mälkki
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() callKyösti Mälkki
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14intel/{i945,pineview},i82801gx: Move enable_smbus() callKyösti Mälkki
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14nb/intel/sandybridge: Drop 'or zero' instancesAngel Pons
Change-Id: Icd0dfdf311ac141992ec6a6026ca92e54e8d2094 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-12intel/e7505: Always enable DIMM compatibility checksKyösti Mälkki
Change-Id: I4862b4f0a029f6f4a1ff7e66cf814fa8f5686d3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12intel/e7505: Remove commented out suspicious codeKyösti Mälkki
Change-Id: I566f016eb4fb710a5246be8b088ab0d2ed00041c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38294 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12intel/e7505,i82801dx: Refactor raminitKyösti Mälkki
Avoid direct enable_smbus() call from northbridge code. Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry()Kyösti Mälkki
Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12intel/e7505,i82801dx: Remove wrapper spd_read_byte()Kyösti Mälkki
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38235 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12asus/{p2b-x,p3b-f},intel/i440bx: Move mainboard_romstage_entry()Kyösti Mälkki
Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12intel/i440bx,i82371: Remove wrapper spd_read_byte()Kyösti Mälkki
Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12asus/p3b-f,intel/i440bx: Move enable/disable_spd() callKyösti Mälkki
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-11nb/intel/sandybridge: Tidy up raminit codeAngel Pons
Some things fit in a single line now that we have a 96-char limit. Tested, does not change the binary of Gigabyte GA-H61MA-D3V. Change-Id: I3bef75291d1ecb2c9c3c74d9e78caf84a1f726aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-10nb/intel/{i945,sandybridge}/bootblock.c: Fix typoElyes HAOUAS
Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38245 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
While we are at it, also: - Rename related variables to match the register names. - Update some comments to better reflect what some registers are about. - Add various FIXME comments on registers that seem to be used wrongly. With BUILD_TIMELESS=1, this commit does not change the coreboot build of: - Asus P8H61-M PRO with native raminit. - Gigabyte GA-H61MA-D3V with native raminit. - Lenovo Thinkpad X230 with native raminit. - Lenovo Thinkpad X220 with MRC raminit. Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-09device,sb/intel: Move SMBus host controller prototypesKyösti Mälkki
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte()Kyösti Mälkki
Change-Id: Ic9554ad2813ee70d0da16857d534aab5e17d808f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09nb/intel/sandybridge: Make MCHBAR arithmetics consistentAngel Pons
Ensure that the operation order is always the same. This results in changes to the binary, but the effective result is the same. Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-06drivers/pc80/rtc: Swap cmos_write32() parameter orderKyösti Mälkki
Make it consistent with the more used cmos_write(). Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-01nb/intel/sandybridge: replace .val_4028 with .io_latencyFelix Held
Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38027 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-01nb/intel/sandybridge/sandybridge.h: Do cosmetic fixesAngel Pons
Change-Id: I212f58bdaee538ad8f0197c0aec742aace1c7921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: Use the MC_BIOS_DATA defineAngel Pons
Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: Make `PM_PDWN_Config` uppercaseAngel Pons
Change-Id: Id37d2367d57ff925476c53bb0edab927c1c768f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: add and use memory thermal configuration registersFelix Held
Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: add and use ME stolen memory and lock bit definesFelix Held
Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BARFelix Held
Change-Id: Ie5a28ceb3d1b684b9c94dcae5b303a4dce75f273 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: add and use more MCHBAR register definesFelix Held
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.hFelix Held
Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: use MESEG register names from datasheetFelix Held
I used register names guessed on what the registers do, since the SNB documentation marked those registers as reserved; the IVB documentation (326765-005) has names for the registers, so I'll use those. Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31src: Remove some romcc workaroundsJacob Garber
Now that romcc is gone, move cmos_post_init() into post.c, and remove some preprocessor workarounds. Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-31northbridge: Add missing include <device/pci_def.h>Elyes HAOUAS
Change-Id: Ib63835d2407bbabbd78b43927f7fbd407ca06a08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37841 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29nb/intel/sandybridge: simplify ME lock and memory enable bit writeFelix Held
Timeless build results in identical image for X230. Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29nb/intel/sandybridge: add and use defines for ME base and mask registersFelix Held
Timeless build results in identical image for X230. Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registersFelix Held
This patch didn't change the resulting binary for an X230 when using TIMELESS_BUILD=1 Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki
There are no symmetrical headerfiles for other arch/ and after ROMCC_BOOTBLOCK and walkcbfs() removal this file ended up empty. Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26nb/haswell/minihd: correct subsystem IDMatt DeVillier
The subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: I74cbba31e93f9bb5b18d3ada780a0f24614ba029 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20{nb,soc}: Replace min/max() with MIN/MAX()Elyes HAOUAS
Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33685 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 10:14:29 +0000