summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x/x4x.h
AgeCommit message (Expand)Author
2020-09-25nb/intel/x4x/x4x.h: Clean up cosmeticsAngel Pons
2020-09-25nb/intel/x4x/iomap.h: Rename to memmap.hAngel Pons
2020-08-04nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons
2020-08-04nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons
2020-08-03nb/intel/x4x: Put host bridge registers into its own fileAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-15nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans
2019-11-13nb/intel/x4x.h: Include stdint.hArthur Heymans
2019-11-04nb/intel/x4x/x4x.h: Include iomap.hArthur Heymans
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
2019-06-21nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps}Elyes HAOUAS
2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-04-30nb/x4x: Get rid of device_tElyes HAOUAS
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2017-12-16nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
2017-05-22nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans
2017-03-21nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans
2017-02-17nb/intel/x4x: Implement resume from S3 suspendArthur Heymans
2017-02-17nb/intel/x4x: Fix raminit on reset pathArthur Heymans
2016-12-03nb/x4x: Fix sticky scratchpad register offsetArthur Heymans
2016-11-28nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculationNico Huber
2016-11-26nb/intel/x4x: Fix and deflate `dimm_config` in raminitNico Huber
2016-11-21nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
2016-09-07nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
2016-01-13northbridge/intel/x4x: clean up includesMartin Roth
2015-12-29northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 00:46:38 +0000