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path: root/src/northbridge/intel/x4x/raminit_ddr23.c
AgeCommit message (Expand)Author
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
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