| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-05-14 | nb/intel/x4x/raminit: Make programming crossclock support DDR3 | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |