Age | Commit message (Expand) | Author |
2021-07-05 | nb/intel/x4x: Use write32p and read32p | Arthur Heymans |
2021-07-05 | nb/intel/x4x: Prepare for x86_64 support | Arthur Heymans |
2021-04-12 | nb/intel/x4x: Refactor sync DLL programming (part 2) | Nico Huber |
2021-04-12 | nb/intel/x4x: Refactor sync DLL programming (part 1) | Nico Huber |
2021-04-12 | nb/intel/x4x: Sort code in program_dll() | Nico Huber |
2021-04-10 | nb/intel/x4x: Use new fixed BAR accessors | Angel Pons |
2021-04-10 | nb/intel/x4x: Correct and use macros for CLKCFG | Angel Pons |
2021-04-10 | nb/intel/x4x: Reflow long lines | Angel Pons |
2021-04-10 | nb/intel/x4x: Correct sync DLL phase search | Angel Pons |
2021-02-10 | nb/intel/x4x: Correct DDR3 turnaround table | Angel Pons |
2021-02-07 | nb/intel/x4x: Constify DDR2 ODT table | Angel Pons |
2021-02-07 | nb/intel/x4x: Clean up RCOMP cosmetics | Angel Pons |
2021-02-07 | nb/intel/x4x: Drop unused first array index | Angel Pons |
2021-02-07 | nb/intel/x4x: Unroll programming RCOMP data group | Angel Pons |
2021-02-07 | nb/intel/x4x: Report if running in async mode | Angel Pons |
2021-02-07 | nb/intel/x4x: Factor out setting Tx DLL tap and PI | Angel Pons |
2021-02-07 | nb/intel/x4x: Correct ctrlset{2,3} register mask | Angel Pons |
2021-02-07 | nb/intel/x4x: Drop commented-out statement | Angel Pons |
2021-01-18 | northbridge/intel/x4x/raminit_ddr23.c: Remove repeated word | Elyes HAOUAS |
2021-01-15 | nb/intel/x4x: Clean up raminit comments | Angel Pons |
2020-10-14 | nb/intel/x4x: Place raminit definitions in raminit.h | Angel Pons |
2020-09-25 | nb/intel/x4x/iomap.h: Rename to memmap.h | Angel Pons |
2020-09-21 | src/northbridge: Drop unneeded empty lines | Elyes HAOUAS |
2020-08-17 | nb/intel/x4x/raminit_ddr23.c: Remove dead assignment | Elyes HAOUAS |
2020-08-05 | src: Use space after 'if', 'for' | Elyes HAOUAS |
2020-08-04 | nb/intel/x4x: Define and use `HOST_BRIDGE` macro | Angel Pons |
2020-06-09 | nb/intel/x4x: Use PCI bitwise ops | Angel Pons |
2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
2020-02-24 | src: capitalize 'RAM' | Elyes HAOUAS |
2019-12-02 | src: Move 'static' to the beginning of declaration | Elyes HAOUAS |
2019-09-06 | nb/intel/x4x/raminit: Move dummy reads after JEDEC init | Arthur Heymans |
2019-07-17 | nb/intel/x4x: Die on invalid memory speeds | Jacob Garber |
2019-06-21 | nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} | Elyes HAOUAS |
2019-06-05 | nb/intel/x4x: Remove variable set but not used | Elyes HAOUAS |
2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
2019-03-04 | device/mmio.h: Add include file for MMIO ops | Kyösti Mälkki |
2019-03-01 | device/pci: Fix PCI accessor headers | Kyösti Mälkki |
2018-12-18 | northbridge: Remove unneeded include <pc80/mc146818rtc.h> | Elyes HAOUAS |
2018-11-19 | src: Add required space after "switch" | Elyes HAOUAS |
2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
2018-10-24 | nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware | Arthur Heymans |
2018-08-04 | x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] | Felix Held |
2018-07-30 | x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] | Felix Held |
2018-06-14 | nb/intel/x4x: Fix a few things in set_enhanced_mode | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Add the option for stacked channel map settings | Arthur Heymans |
2018-05-24 | nb/intel/x4x: Adapt post JEDEC for DDR3 | Arthur Heymans |
2018-05-24 | nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings | Arthur Heymans |
2018-05-24 | nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings | Arthur Heymans |
2018-05-24 | nb/intel/x4x: Implement write leveling | Arthur Heymans |
2018-05-24 | nb/intel/x4x: Add DDR3 JEDEC init | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: DDR3 specific ODT | Arthur Heymans |
2018-05-14 | nb/intel/x4x: Add DDR3 rcomp | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Support programming initials DD3 DLL setting | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Support programming DDR3 timings | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Make programming launch ddr3 specific | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Make programming crossclock support DDR3 | Arthur Heymans |
2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |