| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-05-14 | nb/intel/x4x/raminit: Support programming initials DD3 DLL setting | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x/raminit: Support programming DDR3 timings | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x/raminit: Make programming launch ddr3 specific | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x/raminit: Make programming crossclock support DDR3 | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |