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path: root/src/northbridge/intel/x4x/raminit_ddr23.c
AgeCommit message (Expand)Author
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
2020-08-04nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons
2020-06-09nb/intel/x4x: Use PCI bitwise opsAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-02-24src: capitalize 'RAM'Elyes HAOUAS
2019-12-02src: Move 'static' to the beginning of declarationElyes HAOUAS
2019-09-06nb/intel/x4x/raminit: Move dummy reads after JEDEC initArthur Heymans
2019-07-17nb/intel/x4x: Die on invalid memory speedsJacob Garber
2019-06-21nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps}Elyes HAOUAS
2019-06-05nb/intel/x4x: Remove variable set but not usedElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2018-12-18northbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
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