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path: root/src/northbridge/intel/x4x/raminit_ddr2.c
AgeCommit message (Expand)Author
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2018-02-20nb/x4x/raminit_ddr2: Refactor clock configuration slightlyJonathan Neuschäfer
2017-12-16nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans
2017-08-20nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
2017-07-21nb/intel/x4x: Rework programming DQ and DQS DLL timingsArthur Heymans
2017-07-21sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans
2017-05-24nb/intel/x4x/raminit: Initialise async variableArthur Heymans
2017-05-22nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans
2017-05-21nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUPArthur Heymans
2017-05-20nb/intel/x4x/raminit: Remove very long delayArthur Heymans
2017-05-08nb/x4x/raminit.c: Remove ME locking codeArthur Heymans
2017-03-21nb/x4x: Move checkreset before SPD readingArthur Heymans
2017-03-21nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans
2017-02-17nb/intel/x4x: Implement resume from S3 suspendArthur Heymans
2017-02-17nb/intel/x4x: Fix raminit on reset pathArthur Heymans
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
2016-11-21nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth
2016-11-08nb/x4x/raminit.c: Improve crossclock table cosmeticsArthur Heymans
2016-09-07nb/intel/x4x: Increase MMIO PCI space to 2GiBDamien Zammit
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-09x4x: add non documented vram sizesArthur Heymans
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
2016-01-13northbridge/intel/x4x: clean up includesMartin Roth
2015-12-30northbridge/intel/x4x: Native raminitDamien Zammit
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