| Age | Commit message (Expand) | Author |
|---|
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
| 2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
| 2020-05-01 | src: Remove unused 'include <cpu/x86/cache.h>' | Elyes HAOUAS |
| 2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
| 2020-01-09 | nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte() | Kyösti Mälkki |
| 2019-06-21 | nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} | Elyes HAOUAS |
| 2019-05-29 | src/northbridge: Add missing 'include <types.h>' | Elyes HAOUAS |
| 2019-05-15 | src/northbridge: Remove unneeded include <arch/io.h> | Elyes HAOUAS |
| 2019-05-07 | {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function | Elyes HAOUAS |
| 2019-04-29 | nb/x4x: Use system_reset() and full_reset() | Elyes HAOUAS |
| 2019-04-06 | src: Use include <delay.h> when appropriate | Elyes HAOUAS |
| 2019-03-27 | Move calls to quick_ram_check() before CBMEM init | Kyösti Mälkki |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2019-03-01 | device/pci: Fix PCI accessor headers | Kyösti Mälkki |
| 2019-02-01 | sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() | Kyösti Mälkki |
| 2019-01-10 | mb: Move timestamp_add_now to northbridge x4x | Elyes HAOUAS |
| 2018-12-18 | northbridge: Remove unneeded include <pc80/mc146818rtc.h> | Elyes HAOUAS |
| 2018-11-16 | src: Remove unneeded include <lib.h> | Elyes HAOUAS |
| 2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
| 2018-11-05 | nb/intel/x4x/raminit: Add missing space | Jonathan Neuschäfer |
| 2018-10-15 | nb/intel/x4x: Fix P45 CAPID max frequency | Arthur Heymans |
| 2018-09-16 | nb/intel/x4x: Don't use cached settings if CPU FSB has been changed | Arthur Heymans |
| 2018-06-17 | nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset | Arthur Heymans |
| 2018-06-14 | nb/intel/x4x: Work around a quirk | Arthur Heymans |
| 2018-05-24 | nb/intel/x4x: Add DDR3 JEDEC init | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |
| 2018-05-14 | nb/x4x/raminit: Decode ddr3 dimms | Arthur Heymans |
| 2018-04-28 | nb/intel/x4x: Fix computing page_size | Arthur Heymans |
| 2018-04-17 | nb/intel/x4x: Use SPI flash to cache raminit results | Arthur Heymans |
| 2018-02-22 | device/ddr2,ddr3: Rename and move a few things | Arthur Heymans |
| 2017-12-16 | nb/x4x/raminit: Rewrite SPD decode and timing selection | Arthur Heymans |
| 2017-07-21 | sb/intel/i82801jx: Add correct PCI ids and change names | Arthur Heymans |
| 2017-05-21 | nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP | Arthur Heymans |
| 2017-05-04 | nb/intel/x4x/raminit: Change reset type on incomplete raminit reset | Arthur Heymans |
| 2017-03-21 | nb/x4x: Move checkreset before SPD reading | Arthur Heymans |
| 2017-03-21 | nb/intel/x4x: Fix issues found by checkpatch.pl | Arthur Heymans |
| 2017-01-22 | nb/x4x/raminit: Fix programming dram timings | Arthur Heymans |
| 2016-11-28 | nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation | Nico Huber |
| 2016-11-26 | nb/intel/x4x: Fix and deflate `dimm_config` in raminit | Nico Huber |
| 2016-07-27 | nb/intel/x4x: Fix CAS latency detection and max memory detection | Damien Zammit |
| 2016-07-19 | nb/intel/x4x: Fix CAS latency detection | Damien Zammit |
| 2016-07-09 | nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM | Damien Zammit |
| 2016-06-04 | nb/intel/x4x: Fix unpopulated value | Damien Zammit |
| 2016-01-13 | northbridge/intel/x4x: clean up includes | Martin Roth |
| 2016-01-07 | Correct some common spelling mistakes | Martin Roth |
| 2015-12-30 | northbridge/intel/x4x: Native raminit | Damien Zammit |
