| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-01-24 | nb/intel/x4x: Put stage cache in TSEG | Arthur Heymans |
| 2018-06-05 | nb/intel/x4x: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |
| 2018-05-01 | nb/intel/x4x: Implement both read and write training | Arthur Heymans |
| 2018-04-17 | nb/intel/x4x: Refactor setting default dll settings | Arthur Heymans |
| 2017-08-20 | nb/intel/x4x/raminit: Rework receive enable calibration | Arthur Heymans |
| 2017-02-17 | nb/intel/x4x: Implement resume from S3 suspend | Arthur Heymans |
| 2016-05-31 | nb/intel/x4x: Add DMI/EP init | Damien Zammit |
| 2015-12-30 | northbridge/intel/x4x: Native raminit | Damien Zammit |
| 2015-12-29 | northbridge/intel/x4x: Intel 4-series northbridge support | Damien Zammit |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |