index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
/
intel
/
sandybridge
Age
Commit message (
Expand
)
Author
2012-07-16
Define global uma_memory variables
Kyösti Mälkki
2012-05-29
Sandybridge: Remove remnants of FDT support from MRC cache code
Stefan Reinauer
2012-05-29
Sandybridge: Fix MRC cache calculation
Stefan Reinauer
2012-05-11
Hook up MRC cache update
Stefan Reinauer
2012-05-11
Rework Sandybridge MRC cache handling
Stefan Reinauer
2012-05-08
Clean up #ifs
Patrick Georgi
2012-05-03
Add missing newline to printk in Sandybridge init code
Stefan Reinauer
2012-05-02
Strip quotes from Sandybridge MRC blob
Stefan Reinauer
2012-05-02
Sandybridge: Display platform information early
Vadim Bendebury
2012-05-01
Update Ivybridge GT power meter tables
Duncan Laurie
2012-05-01
Update ivybridge graphics initialization
Duncan Laurie
2012-05-01
Only send ME Dram Init Done message on Sandybridge
Duncan Laurie
2012-05-01
Modify DMI init for IvyBridge
Vincent Palatin
2012-05-01
Fix Sandybridge/Ivybridge mainboards according to code review
Stefan Reinauer
2012-04-30
Sandybridge: Temporarily disable MRC cache finding code
Stefan Reinauer
2012-04-28
Reverse Vendor ID & Device ID for map_oprom_vendev()
Martin Roth
2012-04-27
SMM: Add udelay on Sandybridge systems
Stefan Reinauer
2012-04-05
Add support for Intel Sandybridge CPU (northbridge part)
Stefan Reinauer