aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge/sandybridge.h
AgeCommit message (Expand)Author
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-04-30nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
2018-01-31nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
2017-10-16sandybridge/acpi: remove unnessary check of PCI IDsVagiz Trakhanov
2017-06-15nb/intel/sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
2017-05-19nb/intel/sandybridge: Hide additional nb devicesPatrick Rudolph
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-01-06northbridge/intel: Do not define include guard as 1Edward O'Callaghan
2014-10-16sandybridge: Move common northbridge finalize to northbridge code.Vladimir Serbinenko
2014-10-11acpi: Remove explicit pointer tracking in per-device ssdt.Vladimir Serbinenko
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
2013-05-01boot: remove cbmem_post_handling()Aaron Durbin
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 05:03:50 +0000