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path: root/src/northbridge/intel/sandybridge/sandybridge.h
AgeCommit message (Expand)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
2020-03-20nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-02-01nb/intel/sandybridge: improve indexed register helper macrosFelix Held
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
2020-01-15nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
2020-01-01nb/intel/sandybridge/sandybridge.h: Do cosmetic fixesAngel Pons
2020-01-01nb/intel/sandybridge: Make `PM_PDWN_Config` uppercaseAngel Pons
2020-01-01nb/intel/sandybridge: add and use memory thermal configuration registersFelix Held
2020-01-01nb/intel/sandybridge: add and use ME stolen memory and lock bit definesFelix Held
2020-01-01nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BARFelix Held
2020-01-01nb/intel/sandybridge: add and use more MCHBAR register definesFelix Held
2020-01-01nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.hFelix Held
2020-01-01nb/intel/sandybridge: use MESEG register names from datasheetFelix Held
2019-12-29nb/intel/sandybridge: add and use defines for ME base and mask registersFelix Held
2019-12-29nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registersFelix Held
2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
2019-11-18sb/intel/bd82x6x: Make the pch_enable_lpc hook optionalArthur Heymans
2019-11-18nb/intel/sandybridge: Make the mainboard_early_init hook optionalArthur Heymans
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
2019-11-01nb/intel: Remove unused 'barrier()'Elyes HAOUAS
2019-10-01intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
2019-08-07intel/nehalem,sandybridge: Move stage_cache support functionKyösti Mälkki
2019-06-08nb/intel/sandybridge: Drop iommu.c and rename functionsPatrick Rudolph
2019-05-16nb/intel/sandybridge: Move DMI init codePatrick Rudolph
2019-05-16sb/intel/sandybridge/early_pch: Make DMI init more readablePatrick Rudolph
2019-04-23nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
2019-01-23Drop leftover debug function declarationsKyösti Mälkki
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-04-30nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
2018-01-31nb/intel/*.h: Remove left-over register definitionsPatrick Rudolph
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
2017-10-16sandybridge/acpi: remove unnessary check of PCI IDsVagiz Trakhanov
2017-06-15nb/intel/sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
2017-05-19nb/intel/sandybridge: Hide additional nb devicesPatrick Rudolph
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-01-06northbridge/intel: Do not define include guard as 1Edward O'Callaghan
2014-10-16sandybridge: Move common northbridge finalize to northbridge code.Vladimir Serbinenko
2014-10-11acpi: Remove explicit pointer tracking in per-device ssdt.Vladimir Serbinenko
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
2013-05-01boot: remove cbmem_post_handling()Aaron Durbin
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
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