| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-04 | northbridge/intel: Remove unneeded includes | Elyes HAOUAS |
| 2018-04-16 | nb/intel/sandybridge: support more XMP timings | Dan Elkouby |
| 2017-06-12 | nb/intel/ivybridge: Improve CAS freq selection | Arthur Heymans |
| 2017-04-04 | nb/intel/sandybridge/raminit: Add default values | Patrick Rudolph |
| 2017-04-04 | nb/intel/sandybridge/raminit: Add 100MHz refclock support | Patrick Rudolph |
| 2017-04-04 | nb/intel/sandybridge/raminit: Use Ivy Bridge specific values | Patrick Rudolph |
| 2017-03-27 | nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings | Arthur Heymans |
| 2016-12-16 | nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge | Patrick Rudolph |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |