summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge/raminit.c
AgeCommit message (Expand)Author
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2016-02-04nb/intel/sandybridge/raminit: Fix two dimms per channelPatrick Rudolph
2016-01-29Revert "northbridge/intel/sandybridge: Fix random raminit failures"Vladimir Serbinenko
2016-01-17intel/sandybridge/raminit: fix ODT settingPatrick Rudolph
2016-01-13intel/northbridge/sandy: raminit code cleanupPatrick Rudolph
2015-11-19nb/intel/sandybridge/raminit: Factor out code into toggle_io_resetPatrick Rudolph
2015-11-19nb/intel/sandybridge/raminit: Comment the codePatrick Rudolph
2015-11-18northbridge/intel/sandybridge: Fix random raminit failuresPatrick Rudolph
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-09nb/intel/sandybridge/raminit: Add edge write discovery checkPatrick Rudolph
2015-10-09northbridge/intel/sandybridge: Enable PEG clock-gating on demandPatrick Rudolph
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-06-02cbfs: new API and better program loadingAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
2014-12-02Replace hlt with halt()Patrick Georgi
2014-06-25nehalem sandy ivy: Check cbmem_add() result for MRC dataKyösti Mälkki
2014-05-01Declare recovery and developer modes outside ChromeOSKyösti Mälkki
2014-04-09console: Move newline translation outside console_tx_byteKyösti Mälkki
2014-03-04console: Fix includesKyösti Mälkki
2014-01-15Intel (sandy/ivy): Avoid calling cbmem_initialize() twiceKyösti Mälkki
2014-01-15CBMEM intel: Define get_top_of_ram() once per chipsetKyösti Mälkki
2014-01-12sandybridge: Use calls rather than asm to call to MRC.Vladimir Serbinenko
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
2013-12-23usbdebug: Add option to disable console for romstageKyösti Mälkki
2013-10-14Revert "CBMEM: Always have early initialisation"Kyösti Mälkki
2013-09-21CBMEM: Always have early initialisationKyösti Mälkki
2013-09-11CBMEM x86: Unify get_cbmem_toc()Kyösti Mälkki
2013-07-10usbdebug: Move ehci_debug_info allocationKyösti Mälkki
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
2012-11-07Add missing newline in error messageStefan Reinauer
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
2012-07-30sandybridge: reinitialize usbdebug after MRCSven Schnelle
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 05:19:42 +0000