coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2013-06-22	intel/sandybridge: Locate CBMEM TOC early in ramstage	Kyösti Mälkki
2013-05-01	boot: remove cbmem_post_handling()	Aaron Durbin
2013-04-03	sandybridge: enable ROM caching	Aaron Durbin
2013-03-23	resources: introduce reserved_ram_resource()	Aaron Durbin
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-02-28	Drop CONFIG_WRITE_HIGH_TABLES	Stefan Reinauer
2013-02-14	sconfig: rename lapic_cluster -> cpu_cluster	Stefan Reinauer
2013-02-14	sconfig: rename pci_domain -> domain	Stefan Reinauer
2012-11-28	Remove assembly coded log2 function	Ronald G. Minnich
2012-08-08	Cleanup coreboot memory table includes	Kyösti Mälkki
2012-08-07	Sandy/Ivy Bridge and Cougar/Panther Point: Fix names	Stefan Reinauer
2012-08-01	Intel and GFXUMA: drop redundant use of lb_add_memory_range()	Kyösti Mälkki
2012-08-01	Intel Sandybridge and UMA: use mmio_resource()	Kyösti Mälkki
2012-08-01	Intel Sandybridge: add reserved memory as resources	Kyösti Mälkki
2012-07-24	Ivybridge: fix workaround and enable PAIR	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-07-24	SandyBridge: Add another PCI device ID for northbridge	Walter Murphy
2012-07-16	Define global uma_memory variables	Kyösti Mälkki
2012-05-11	Hook up MRC cache update	Stefan Reinauer
2012-05-11	Rework Sandybridge MRC cache handling	Stefan Reinauer
2012-05-08	Clean up #ifs	Patrick Georgi
2012-05-01	Modify DMI init for IvyBridge	Vincent Palatin
2012-04-05	Add support for Intel Sandybridge CPU (northbridge part)	Stefan Reinauer