coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-03-18	nb/intel/sandybridge: Tidy up code and comments	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2020-01-10	nb/intel/sandybridge: Add a bunch of MCHBAR defines	Angel Pons
2020-01-01	nb/intel/sandybridge: add and use ME stolen memory and lock bit defines	Felix Held
2020-01-01	nb/intel/sandybridge: use MESEG register names from datasheet	Felix Held
2019-12-29	nb/intel/sandybridge: add and use defines for ME base and mask registers	Felix Held
2019-12-29	nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers	Felix Held
2019-12-19	src/northbridge: Remove unused <stdlib.h>	Elyes HAOUAS
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
2016-12-08	nb/intel/sandybridge: Lock PAVPC	Dennis Wassenberg
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-08-09	intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses	Kyösti Mälkki
2013-07-10	Drop some duplicates of PCI-e config functions	Kyösti Mälkki
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-04-05	Add support for Intel Sandybridge CPU (northbridge part)	Stefan Reinauer