coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-07-13	intel sandybridge: add VGA pci device id	Patrick Rudolph
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-10-23	intel/sandybridge: Add VGA pci device ID 0x0162	Damien Zammit
2014-10-16	sandybridge: Move common northbridge finalize to northbridge code.	Vladimir Serbinenko
2014-08-03	sandy/ivybridge: Make UMA size configurable.	Vladimir Serbinenko
2013-07-10	Drop some duplicates of PCI-e config functions	Kyösti Mälkki
2013-07-04	intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT	Kyösti Mälkki
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-01-14	Support for Celeron 1007U	Stefan Reinauer
2012-07-25	ELOG: Add support for a monotonic boot counter in CMOS	Duncan Laurie
2012-07-24	ELOG: Fix boot count increment for non-wake case	Duncan Laurie
2012-07-24	Ivybridge: fix workaround and enable PAIR	Duncan Laurie
2012-07-24	Drop (empty) sandybridge_late_initialization()	Stefan Reinauer
2012-04-05	Add support for Intel Sandybridge CPU (northbridge part)	Stefan Reinauer