| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-05-13 | nb/intel/sandybridge: Migrate MRC settings to devicetree | Patrick Rudolph |
| 2016-06-12 | nb/intel/raminit (native): Read PCI mmio size from devicetree | Patrick Rudolph |
| 2016-02-28 | northbridge/intel: add missing #include guards | Iru Cai |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-02-17 | sandybridge/raminit: Get max mem clock from devicetree | Alexandru Gagniuc |
| 2014-09-13 | intel/gma: consolidate vbt code | Vladimir Serbinenko |
| 2014-07-29 | ivybridge: LVDS gfx init. | Vladimir Serbinenko |
| 2014-07-08 | northbridge: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-08-22 | Auto-declare chip_operations | Kyösti Mälkki |
| 2012-05-01 | Update ivybridge graphics initialization | Duncan Laurie |
| 2012-04-05 | Add support for Intel Sandybridge CPU (northbridge part) | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |