| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-01-15 | CBMEM intel: Define get_top_of_ram() once per chipset | Kyösti Mälkki |
| 2014-01-15 | sandybridge: Allow skipping mrc.cache | Vladimir Serbinenko |
| 2013-06-28 | Add support to enable/disable builtin GbE (again) | Stefan Reinauer |
| 2013-06-20 | sandybridge: Store MRC cache in CBFS | Patrick Georgi |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-11-27 | Remove AMD special case for LAPIC based udelay() | Patrick Georgi |
| 2012-11-27 | Get rid of drivers class | Patrick Georgi |
| 2012-11-12 | Initial IGD OpRegion implementation | Stefan Reinauer |
| 2012-05-11 | Rework Sandybridge MRC cache handling | Stefan Reinauer |
| 2012-05-02 | Strip quotes from Sandybridge MRC blob | Stefan Reinauer |
| 2012-05-02 | Sandybridge: Display platform information early | Vadim Bendebury |
| 2012-04-27 | SMM: Add udelay on Sandybridge systems | Stefan Reinauer |
| 2012-04-05 | Add support for Intel Sandybridge CPU (northbridge part) | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
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