| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-01 | nb/intel/pineview: Don't use PCI operations on the pci_domain device | Arthur Heymans |
| 2018-06-29 | sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables | Arthur Heymans |
| 2018-05-08 | {mb,nb,soc}: Remove references to pci_bus_default_ops() | Nico Huber |
| 2018-04-30 | nb/intel/pineview: Get rid of device_t | Elyes HAOUAS |
| 2017-06-28 | cpu/intel/pineview: Include speedstep | Arthur Heymans |
| 2017-04-24 | nb/intel/pineview: Move to early cbmem | Arthur Heymans |
| 2017-01-06 | nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> | Arthur Heymans |
| 2016-07-15 | intel/pineview: Do not use scratchpad register for ACPI S3 | Kyösti Mälkki |
| 2016-07-14 | nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration | Jonathan Neuschäfer |
| 2016-01-28 | nb/intel/pineview: Native VGA init (CRT) | Damien Zammit |
| 2016-01-20 | nb/intel/pineview: Use macro names for memory base registers | Damien Zammit |
| 2015-12-02 | northbridge/intel/pineview: Add remaining boilerplate code for northbridge | Damien Zammit |
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index : coreboot.git | |
| my copy of coreboot | User & |
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