| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
| 2019-08-07 | northbridge/intel: Rename ram_calc.c to memmap.c | Kyösti Mälkki |
| 2019-08-03 | intel/i945,gm45,pineview,x4x: Move stage cache support function | Kyösti Mälkki |
| 2019-05-25 | nb/intel/pineview: Use MTRR as a proxy for proper reset | Arthur Heymans |
| 2019-05-25 | nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2019-01-24 | nb/intel/pineview: Put stage cache in TSEG | Arthur Heymans |
| 2019-01-14 | nb/intel/pineview: Move the boilerplate mainboard_romstage_entry | Arthur Heymans |
| 2018-06-05 | nb/intel/pineview: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2016-01-28 | nb/intel/pineview: Native VGA init (CRT) | Damien Zammit |
| 2015-12-02 | northbridge/intel/pineview: Add native raminit | Damien Zammit |
| 2015-12-02 | northbridge/intel/pineview: Add remaining boilerplate code for northbridge | Damien Zammit |
| 2015-11-24 | northbridge/intel/pineview: Add minimal Pineview northbridge | Damien Zammit |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |