| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-05 | cpu/intel/model_2065x: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-04 | nb/intel: Use postcar_frame_add_romcache() | Nico Huber |
| 2018-05-31 | {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate | Nico Huber |
| 2018-04-09 | intel/nehalem post-car: Use postcar_frame for MTRR setup | Kyösti Mälkki |
| 2016-11-11 | intel post-car: Separate files for setup_stack_and_mtrrs() | Kyösti Mälkki |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-01-27 | CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM | Kyösti Mälkki |
| 2014-06-18 | intel/nehalem: Add get_top_top_ram() in ramstage | Kyösti Mälkki |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |