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This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Deduplicate a condition and reflow some lines.
Tested on HP ProBook 6550b, still reaches TianoCore payload.
Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.
The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.
Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).
Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.
Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HECI stuff is in the southbridge, so put the code in there. Rename the
file to match the name of the function it provides.
Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove all northbridge dependencies in the `setup_heci_uma()` function.
Update its signature to not pull in raminit internals and drop a dummy
read that doesn't have any side-effects (it's probably a leftover from
a replay of vendor firmware). This code will be moved into southbridge
scope in a follow-up.
Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove the temporary `raminit_heci.c` include and make it a proper
compilation unit. Export the `setup_heci_uma()` function.
Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move HECI code out of raminit.c into a separate raminit_heci.c file. To
preserve reproducibility, use a temporary .c include. This will be gone
in a follow-up.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Leftover from using UDELAY_LAPIC on these platforms.
Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I5d3af659255548e84ef676387ca994588c69438c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I617fea8a09049e9a87130640835ea6c3e2faec60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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As long as there is only one PCI segment we do not need
more complicated MCFG generation.
Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I7e37d32251fa3dcc64aec62dd2d814463c4a9999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55580
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 4447996cc582d2c8745802b84b1f5a635e33a22a.
It looks like the patch repurposed the `memory_reserved_for_heci_mb`
variable as an indicator if the ME firmware is fine. The change to
setup_heci_uma() made it bail out early, even though the implementation
is obviously prepared to set things up even if the requested UMA
size is 0. This also leaves the code in an inconsistent state: The
second if's condition is always true.
Resolves: https://ticket.coreboot.org/issues/305
Change-Id: Ie5a98be3f660078a85a79b5551e86f90f148974f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ia0a086bd28b796d2cbe1c7a056922721c95612b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51868
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Except for some formatting differences, the macros are equivalent.
Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 56823f53dc6de5a804f7c88b9f24847133ddc876 (nb/intel/ironlake:
Rewrite early QPI init) rewrote this part, but the or-value is missing
one zero. Correct this magic value to align with MRC binaries.
Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.
Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead, convert the struct to a union and pass in a pointer to it.
Tested on out-of-tree HP ProBook 6550b, still boots.
Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows booting without ME firmware, even though the 30-minute
auto-shutdown still happens. Without this patch, an HP ProBook 6550b
cannot get past the `setup_heci_uma` function call.
Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.
Tested on out-of-tree HP 630, still boots.
Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.
Tested on out-of-tree HP 630, still boots.
Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.
Tested on out-of-tree HP 630, still boots.
Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Transform the existing functions so that their functionality does not
overlap. Also, deduplicate printing these values in debug builds.
Tested on out-of-tree HP 630, still boots.
Change-Id: I3f50dcf56284c9648b116bc5aacc0adf2d863b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49583
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The platform performs a CPU-only reset after initializing QPI (QuickPath
Interconnect) and before actually performing raminit. The state is saved
in the sticky scratchpad register at MCHBAR + 0x2ca8.
Relocate some QuickPath init to a separate file. All moved functions are
only used within QPI init code, and had to be relocated in one commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I14c5671dfc611209e28f25f38b4e82d11aef88ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49580
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Introduce the `get_bits_420` helper to avoid doing the same thing in
three different ways, and also correct a related register write.
Tested on out-of-tree HP 630, still boots.
Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Dummy reads followed by writes are actually read-modify-write operations
in disassembled binaries. Handling of the scratchpad register 0x2ca8 is
still nonsense, but that should be taken care of in a separate commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We only need to toggle one bit at a time. Introduce `rmw_500` to
simplify the code. The rank population doesn't seem to matter.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bits are already cleared in southbridge_detect_s3_resume().
Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Was copy-pasted from bd82x6x and no mainboard actually needs it.
The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.
Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Drop casts to prevent pointer arithmetic and for consistency with other
platforms. These macros will be factored out in a subsequent commit.
Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49747
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This partially reverts:
- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e
It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.
Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.
With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.
Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use defined RCBAx macros over readX/writeX calls.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.
Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All callsites of `rmw_1d0` use the same `flag` value.
Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Fixed resources should not overlap.
Change-Id: I7a70f5475c1d701db2cb8cbea659bacf6d0c52ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This cosmetic change does 2 things:
- change bitwise shifting to division
- Make the division by / KiB explicit for fixed legacy ranges like
0xa0000-0xbffff.
Change-Id: If4e05f496abc05e06a944b244824376f3937a57b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ic5a49a81a886aecde0fbaae3ecfa6b0504a4e3ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ic2582dbf70e11e0566ba525c72300a6248807512
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Given the lack of documentation for this platform, having this info
in coreboot logs (e.g. from board_status) can be pretty useful.
Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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For a long time, second parameter 'stop' has been
ignored. The tested range is within 1 MiB above 'start'.
Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.
Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.
Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.
Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48562
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move all memory map definitions into a separate header.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45379
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to wrap these macros with casts. Removing them allows
dropping more casts in `early_init.c`.
To avoid binary changes the casts are put into the
{MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach
the right memory locations.
Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
The current coreboot code seems to be able to change the device ID
of the host bridge, but it seems to be missing a warm reset so that
the device ID changes. Account for the 'mysterious' device IDs in
the northbridge driver, so that booting an OS has a chance to work.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Although only Arrandale is known to work, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code is known to work on processors other than just i7's. Also, use
the northbridge's name (Ironlake) in place of the CPU's (Arrandale).
Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ib1da100ba24de30256b3e80e380deb9c9ef4879e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I4c4b40b2b4f54b7756b8485dad80a1b4786270f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Drop unused includes and add missing <types.h>.
Change-Id: Ifefe81d4727d67ea702c5e24527f80a0614aa396
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use correct datasize to compile on x86_64.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7632
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ie0198a44589271de0335a51937e95662db891d98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The only raminfo field it needs is `memory_reserved_for_heci_mb`. So,
pass in that value directly. As it's read-only, make it const as well.
Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45365
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to have it in raminfo. Also, bump MRC_CACHE_VERSION.
Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45364
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It has been read twice already, so don't read it a third time.
Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Some of the HECI functions do not need raminfo at all.
Change-Id: If0720fa87e5e18820db77a1b61bcdb42ecc538fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.
Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This macro is unused, and RCBA is located in the PCH. Drop it.
Change-Id: Id7c095496360bbe96dc2a36dcc557a1481c02c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45347
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes commit e1d1fe454cf27d6b1c2ef5625f1cefc1a9c6ec9d
initialize 'reply.command'.
The compiler now optimized away the final condition, that checks
the result of heci message, resulting in a binary that always
calls die().
Fix that behaviour by using volatile.
Tested on Lenovo T410: Boots again into Linux.
Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.
TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.
Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic587231b57c51db592c1647de138a67c55161e58
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The PRM does not describe the relevant bits, but Linux's i915 driver
handles these bits the same way for both Ironlake and Sandy Bridge.
Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6afea5c102299e570378a1656d3dcd329a373399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Other northbridges have a `decode_pcie_bar` function. Since it's not
needed anywhere else, keep it as a static function for now.
Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This brings Ironlake closer to Sandy Bridge.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43687
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I44db564c757647f493e92d35602178ef8b722517
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Like the QPI Link device, there can be more of these devices on
multi-socket platforms. So, name it Physical Layer 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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