summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/ironlake/early_init.c
AgeCommit message (Expand)Author
2021-02-10nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
2020-12-07nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons
2020-08-03nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons
2020-07-24nb/intel/ironlake: Move southbridge code to ibexpeakAngel Pons
2020-07-02nb/intel/ironlake: Clean up code style (except raminit)Angel Pons
2020-07-01nb/intel/ironlake: Use `pci_update_config32()`Angel Pons
2020-07-01nb/intel/ironlake: Simplify BAR handlingAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 22:51:35 +0000