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path: root/src/northbridge/intel/haswell/acpi
AgeCommit message (Expand)Author
2021-02-16nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki
2021-02-12nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
2021-02-06intel: Define `RCBA_LENGTH` in Kconfig and use itAngel Pons
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
2020-11-13nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons
2020-11-13nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
2020-11-13nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons
2020-11-13nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVENAngel Pons
2020-11-13haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons
2020-11-04nb/intel/haswell: Place CTDP ASL code in a separate scopeAngel Pons
2020-11-04nb/intel/haswell/acpi: Align with BroadwellAngel Pons
2020-08-04nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons
2020-07-08nb/intel/haswell/acpi: Update to ASL 2.0 syntaxAngel Pons
2020-07-08nb/intel/haswell/acpi: Fix host bridge registersAngel Pons
2020-06-03northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge...Furquan Shaikh
2020-06-03northbridge/intel/haswell: Update hostbridge.asl to ASL2.0Furquan Shaikh
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-31drivers/intel/gma: fold gma.asl into default_brightness_levels.aslMatt DeVillier
2020-03-25drivers/intel/gma/acpi: Add Kconfigs for backlight registersNico Huber
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-06nb/intel/haswell/peg: Add PEG driver stubChris Morgan
2019-11-04nb/intel: Use defined DEFAULT_RCBAElyes HAOUAS
2019-10-24acpi: Drop wrong _ADR objects for PCI host bridgesElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
2018-11-01sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick
2017-06-27nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2016-09-20northbridge/intel/haswell: Add space around operatorsElyes HAOUAS
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
2015-10-12gma: Consolidate Intel IGD ACPI code some moreNico Huber
2015-05-28igd.asl rewriteVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-01intel: Correct MMIO related ACPI table settingsDave Frodin
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2014-07-17northbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-02-24intel/*/acpi: Increase range length of MCHBAR buffer to 32 kBPaul Menzel
2013-12-07haswell: Add ACPI support for Controllable TDPDuncan Laurie
2013-03-20haswell: drop memory reservation for sandybridge GPU bugDuncan Laurie
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
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