coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-07	northbridge/intel: Rename ram_calc.c to memmap.c	Kyösti Mälkki
2019-07-09	arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class	Kyösti Mälkki
2019-04-21	cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
2018-06-05	cpu/intel/haswell: Switch to POSTCAR_STAGE	Arthur Heymans
2018-02-06	nb/intel/haswell: Use the common MRC cache driver	Arthur Heymans
2016-03-11	northbridge/intel: move mrccache.c of sandybridge + haswell to common	Alexander Couzens
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-07	intel: Do not hardcode the position of mrc.cache	Alexandru Gagniuc
2015-07-13	x86: flatten hierarchy	Stefan Reinauer
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-29	kbuild: automatically include northbridges	Stefan Reinauer
2015-03-30	Update hex values to CBFS binary name types in Makefiles	Martin Roth
2015-01-10	haswell: Fix MRC cache to use CBFS	Kyösti Mälkki
2014-11-20	Replace includes of build.h with version.h	Kyösti Mälkki
2014-10-16	ACPI: Remove CONFIG_GENERATE_ACPI_TABLES	Vladimir Serbinenko
2014-01-15	CBMEM intel: Define get_top_of_ram() once per chipset	Kyösti Mälkki
2013-12-12	HDA: Enable Mini-HDA and fix up PCH-HDA init	Duncan Laurie
2013-05-07	haswell: use tsc for udelay()	Aaron Durbin
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin