summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/gm45/northbridge.c
AgeCommit message (Expand)Author
2023-07-14nb/intel/gm45: Rework nb resource readingArthur Heymans
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
2022-12-01nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
2022-10-06treewide: use predicate to check if pci device is on n-th busFabio Aiuto
2022-09-14nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
2022-05-24nb/intel/i945,gm45: Use incrementing index with fixed resourceKyösti Mälkki
2022-05-13nb/intel/gm45: Enable 64bit supportArthur Heymans
2022-05-13nb/intel/gm45: Allow for PCI BARs above 4GArthur Heymans
2021-01-30nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-18nb/intel/gm45: Reserve MMIO and firmware memory below 1MiBNico Huber
2020-08-04nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons
2020-08-04nb/intel/gm45: Use PCI bitwise opsAngel Pons
2020-05-26nb/intel: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-06northbridge: Remove unused include <device/pci.h>Elyes HAOUAS
2019-12-31northbridge: Add missing include <device/pci_def.h>Elyes HAOUAS
2019-12-19src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
2019-08-15intel/smm/gen1: Rename header fileKyösti Mälkki
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-01-23nb/intel/gm45: Use parallel MP initArthur Heymans
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
2019-01-04device: Replace ugly cases of dev_find_slot()Kyösti Mälkki
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
2018-12-03nb/intel/gm45: Correctly cache TSEGArthur Heymans
2018-11-25nb/intel/gm45/northbridge.c: Check for NULL pointersArthur Heymans
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-04-30nb/intel/gm45: Get rid of device_tElyes HAOUAS
2018-03-28nb/intel/gm45: Allocate a 8M TSEG regionArthur Heymans
2017-10-03nb/intel/gm45: Remove UMA alignment optimizationNico Huber
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
2016-09-20northbridge/intel/gm45: Add space around operatorsElyes HAOUAS
2016-02-09Revert "northbridge/intel/peg: Disable unused ports"Nico Huber
2016-02-04northbridge/intel/peg: Disable unused portsPatrick Rudolph
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-11-12gm45: Don't crash if less than 4G of RAM are present.Vladimir Serbinenko
2014-11-01northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-15gm45: Convert to per-device ACPIVladimir Serbinenko
2014-08-17gm45: Declare BIOS memory as RAM.Vladimir Serbinenko
2014-08-16gm45: Decrease MTRR usageVladimir Serbinenko
2014-08-14gm45: Set acpi_slp_type only once.Vladimir Serbinenko
2014-08-12gm45: Move S3 detection to enable stage.Vladimir Serbinenko
2014-06-18northbridge/intel: Drop use of set_top_of_ram()Kyösti Mälkki
2013-09-11CBMEM northbridges: Remove references to global high_tables_baseKyösti Mälkki
2013-07-10Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
2012-11-27intel/gm45: new northbridgePatrick Georgi
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 16:46:02 +0000