coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-21	intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor	Kyösti Mälkki
2019-03-16	drivers/intel/fsp1_0: Deduplicate code	Patrick Rudolph
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-06	device: Use pcidev_path_on_root()	Kyösti Mälkki
2018-10-22	intel: Use CF9 reset (part 1)	Patrick Rudolph
2018-07-09	src/northbridge: Use "foo bar" instead of "foo bar"	Elyes HAOUAS
2017-04-25	lib: provide clearer devicetree semantics	Aaron Durbin
2016-09-20	northbridge/intel/fsp_rangeley: Add space around operators	Elyes HAOUAS
2016-08-31	northbridge/intel: Add required space before opening parenthesis '('	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-14	Revert "Remove FSP Rangeley SOC and mohonpeak board support"	Martin Roth
2015-10-03	Remove FSP Rangeley SOC and mohonpeak board support	Alexandru Gagniuc
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-24	fsp: Move fsp to fsp1_0	Marc Jones
2015-02-06	FSP & CBMEM: Fix broken cbmem CAR transition.	Martin Roth
2015-01-31	intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP	York Yang
2014-10-19	x86 romstage: Move stack just below RAMTOP	Kyösti Mälkki
2014-07-30	northbridge/intel: Add fsp_rangeley northbridge support	Martin Roth