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Commit message (
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Author
2016-01-24
nb/amd/mct_ddr3: Properly set MR0 WR value
Timothy Pearson
2016-01-24
northbridge/amd/amdmct: Add termination and timing values for C32 sockets
Timothy Pearson
2015-12-01
nb/amd/mct_ddr3: Add Family 15h tristate enable codes
Timothy Pearson
2015-11-24
northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination debug output
Timothy Pearson
2015-11-16
northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
Timothy Pearson
2015-11-16
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Timothy Pearson
2015-11-16
nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs
Timothy Pearson
2015-11-14
northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Timothy Pearson
2015-11-02
cpu/amd: Add initial AMD Family 15h support
Timothy Pearson
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-26
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
Timothy Pearson
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2011-01-20
For Cx, each ChipSel need to be sent MR command.
Zheng Bao
2011-01-06
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Zheng Bao
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao