coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-03-03	northbridge/amd/amdmct: Add revision D to K10 revision mask list	Timothy Pearson
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-09-24	Add AMD Family 10h PH-E0 support	QingPei Wang
2011-03-28	Add AMD C32 support.	Zheng Bao
2011-02-28	Improving BKDG implementation of P-states,	Xavi Drudis Ferran
2011-02-28	Improving BKDG implementation of P-states,	Xavi Drudis Ferran
2011-02-28	Improving BKDG implementation of P-states,	Xavi Drudis Ferran
2011-01-06	Fix some settings fo AMD MCT. It is based on BIOS test suite.	Zheng Bao
2010-08-22	Include RB_C3 in erratum 346	Xavi Drudis Ferran
2010-08-22	Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.	Xavi Drudis Ferran
2010-04-24	Trivial. Fix a space to tab.	Zheng Bao
2010-04-23	DDR3 support for AMD Fam10.	Zheng Bao
2010-03-10	The following patch implements Opteron Fam 10 rev D (aka Istanbul)	Arne Georg Gleditsch
2009-08-24	This patch is about the DA-C2 and RB-C2. Chip with install processor	Zheng Bao
2009-05-14	Update equivalent processor revision ID to load latest microcode patches and	Marc Jones
2008-07-23	Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).	Marc Jones
2008-04-22	Add early MSR and PCI register initialization.	Marc Jones
2008-01-18	Please bear with me - another rename checkin. This qualifies as trivial, no	Stefan Reinauer
2007-12-19	Initial AMD Barcelona support for rev Bx.	Marc Jones