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New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Producer and consumer of these buffers now appear in same file.
Also add test for uninitialized NonVolatileStorage in SPI.
Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This save/restore facility operates on the same datablock.
Change-Id: I6e1f176adc2addbf2659c724f94c1b8d46d4838f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19026
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Only guard the parts that are problematic for romstage.
Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup
work, it will need OemS3LateRestore.
Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19025
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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A problem around CAR teardown time may result with missing
training results at the time we want to save them.
Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.
Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18534
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Definitions are not part of ACPI S3 feature, nor do
they require any AGESA headers so move them to a
better location.
Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93.
Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.
Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Commit 300caced9 introduced stack overflow when HAVE_ACPI_RESUME
is selected as the temporary storage for MTRRs is 4KiB.
Change-Id: I993df6abc04436fb135822729c4931c5c7496e5a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11633
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10583
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with
S3_DATA_BLOCK.
Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10526
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There is no need to backup VolatileStorage in SPI flash at all.
At the time we need it, we have CBMEM available.
Change-Id: If0ca57b314140a833d6d59fe9e236e07816f05a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10317
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Use separate CBMEM allocations for stack and heap on S3 resume path.
The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved
out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE
used on non-resume paths.
Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10316
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Use function prototypes that match more closely with the structure
of other OEM hooks in agesawrappers.
Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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This is more agesawrapper-related code than CPU.
Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10295
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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