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To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.
Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.
Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
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Change-Id: I3fdd2a9f981592112998d74ce4cfe4850d8fab31
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7288
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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Add the northbridge file for AMD's new Mullins and Steppe Eagle
processor family. Since the processor family name is not the
same across AMD's sales and marketing channels, I have elected
to use part of the processor ID as the family name. The intent
is to reduce confusion since the processor ID is the same for
both families. This northbridge support has only been validated
on the AMD Embedded variants ("Steppe Eagle").
The AGESA wrappers in coreboot have a function that is intended to
mirror the UMA memory allocation performed during memory initialization
by AGESA. Update the Steppe Eagle memory allocation to mimic the
memory reservation done inside the AGESA BLOB.
Change the default CBMEM address, the default video BIOS device ID,
and a couple of other defaults to match changes in coreboot community
code.
The northbridge chip.h specifies how many processor sockets, how
many channels, and how many DIMM slots are supported by the
northbridge. Steppe Eagle does not permit multisocket systems
and has only one memory controller channel.
Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6678
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
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