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2020-10-23mb/google/zork: update telemetry settings for morphiusKevin Chiu
Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD Slope: 62852 -> 62641 SOC Slope: 28022 -> 28333 BUG=b:170531252 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-23mb/google/zork/woomax: Adjust disconnect thresholdRob Barnes
The disconnect voltage needs to be adjusted up because the HS DC voltage level is 0xF. BUG=b:170879690 TEST=Servo_v4 USB hub functions BRANCH=zork Change-Id: If8662015a45c57e457b4593e55af888084842f58 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-23mb/google/dedede: Update the flash ROM layout for RW regionsKarthikeyan Ramasubramanian
RW_LEGACY region needs to be 1 MiB to accommodate any alternate firmware. Hence update the flash ROM layout as below: * Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to RW_LEGACY region so that it grows to 1 MiB. * Remove VBLOCK_DEV region which is not used. * Re-size the ELOG region to 4 KiB since that is the maximum size of the ELOG mirror buffer. * Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that size is used in those regions. * Resize SHARED_DATA region to 4 KiB since no more than that size is used in that region. * Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB. BUG=b:167943992, b:167498108 TEST=Build and boot to OS in Drawlat. Ensure that the firmware test setup and flash map test are successful. Ensure that the event logs are synced properly between reboots. Ensure that the suspend/resume sequence is working fine. Ensure that the ChromeOS firmware update completes successfully for the boot image with updated flash map and the system boots fine after the update. Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23mb/google/dedede/var/drawcia: Add MIPI camera supportWisley Chen
To support mipi WFC. 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 in devicetree BUG=b:163879470, b:171258890, b:170936728, b:167938257 TEST=Build and boot to OS. Capture frames using camera app. Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44939 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23sc7180: enable RECOVERY_MRC_CACHEShelley Chen
Enable caching of memory training data for recovery as well as normal mode because memory training is taking too long in recovery as well. This required creating a space in the fmap for RECOVERY_MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=Run power_state:rec twice on lazor. Ensure that on first boot, memory training occurs and on second boot, memory training is skipped. Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22dedede: Create metaknight variantTim Chen
Create the metaknight variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:169813211 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_METAKNIGHT Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22mb/google/asurada: Add Chrome OS GPIOsHung-Te Lin
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs. BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22mb/google/asurada: enable SPI devicesNicolas Boichat
Configure and initialize EC and TPM on Asurada. BUG=none TEST=boot asurada Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/offNico Huber
The 0x30 register is eventually controlled by coreboot's pnp_enable_resources() based on the on/off setting. Other register settings were grouped with their respective "virtual" LDN, where possible. Note, this temporarily breaks LDN 8 settings, as coreboot will ignore configuration for disabled devices. Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registersNico Huber
The `io` statement will prepare a 16-bit write, hence use `irq` for miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge 0x61 writes into 0x60). Note, using `irq` is still just a hack as these are neither I/O nor IRQs, but it's common practice in coreboot. Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/asus/f2a85-m_pro: Enable keyboard controller in devicetreePaul Menzel
The mainboard has a PS/2 port, so enable the keyboard controller in the devicetree. The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux, probably as ACPI code still needs to be added. Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/google/zork: update USB 2.0 controller Lane Parameter for morphiusKevin Chiu
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment". COMPDISTUNE0: 0x3->0x7 TXVREFTUNE0: 0x6->0xf BUG=b:162614573 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 registers are set correctly 3. test with servo v4 type-c, it's working expectedly. 4. U2 SI pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/google/zork: Update telemetry settings for morphiusKevin Chiu
Correct the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. BUG=b:168265881 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21mb/google/dedede: drop obsolete ISST workaroundMichael Niewöhner
Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21mb/asus/f2a85-m_pro: Enable UART A in Super I/OPaul Menzel
Currently, the serial console does not work. With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below. Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40. Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`. coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31 APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET `AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues. PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 […] done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... CPU_CLUSTER: 0 init […] Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits. TEST=Receive (some) coreboot log messages over the serial console. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21mb/supermicro/x11-lga1151-series: Follow up GPIO macro changesPatrick Georgi
Following commit f50ea988b a couple of symbols are gone, so follow up that change for this board as well. Change-Id: I09fd3a107447eb45bb46b7f0f821377943f140b2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21mb/google/dedede/variants/drawcia: update PL1 max and min power valuesSumeet R Pawnikar
Update PL1 max and min power values BUG=None BRANCH=None TEST=build and verify on dralat system Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/google/volteer/var/terrador: Configure board specific DPTF parametersDavid Wu
Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20mb/google/volteer/variants/lillipup: add generic SPDsNick Vaccaro
Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mb/google/dedede: Add P-sensor for Botenalec.wang
Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/google/dedede: add PEN for Botenalec.wang
Update devicetree of boten that enable stylus BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFSAngel Pons
I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20mb/google/asurada: Init dram in romstageHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/siemens/chili: Add Chili variantNico Huber
This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/siemens/chili: Add new mainboardThomas Heijligen
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19mb/google/octopus/variants/ampton: Add G2Touch touchscreen supportJames Chao
BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-19superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons
There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency"Rob Barnes
This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51. Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible. TEST=Boot Dalboz BUG=b:159823235, b:169940175 BRANCH=zork Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-19mb/google/dedede/var/waddledee: Enable GPIO based I2C MultiplexerKarthikeyan Ramasubramanian
The camera sensor component chosen for UFC and WFC have an address conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also configure the GPIO that is used as select line. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19mb/google/volteer: Enable USB4 retimer driverDuncan Laurie
Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/google/kukui: Support SKU from camera EEPROMHung-Te Lin
To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen
Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/purism/librem_skl: Clean up FSP-M RCOMP settingsAngel Pons
There's no need to use static functions to fill these settings in. Also, add missing include for <stdint.h> and initialize `mem_cfg` in one line. Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46252 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/zork/var/vilboz: update dptc stapm timeJohn Su
Update dptc setting: Stapm_time_constant 1400 BUG=b:170696020 BRANCH=zork TEST=emerge coreboot and check "Stapm_time_constant" Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-17mb: AMD CIMx boards: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17AGESA mb: Replace tab with space in macro definition for consistencyPaul Menzel
With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner
This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-16mb/google/zork: disable eMMC per FW_CONFIG for berknipKevin Chiu
Berknip has SSD/eMMC SKU, we should turn off eMMC　if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-16mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik
This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/google/volteer: Disable HybridStorageMode for volteer baseboardShaunak Saha
HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/adlrvp: Add ADL-P mainboard ASL codeSubrata Banik
Add required ASL files into dsdt.asl TEST=Dump and disassemble DSDT and verify all ACPI devices are present. Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/adlrvp: Add ADL-P ramstage mainboard codeSubrata Banik
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/purism/librem_skl: Drop DQ and DQS byte mapsAngel Pons
These settings are not necessary for DDR4 and can be dropped. Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-14mb/google/dedede/var/madoo: Update DPTF settingJohn Su
Add tcc, critical, passive policy, and pl values from thermal team. BUG=b:169215576 TEST=build and verify by thermal tool Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-10-14mb/intel/tglrvp: Enable Pcie WWAN m.2Bora Guvendik
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration. BUG=none TEST=Boot to OS, check WWAN functionality Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/zork: Enable wake on wireless lanRob Barnes
Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up BRANCH=zork Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)Tony Huang
Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()Elyes HAOUAS
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniformElyes HAOUAS
Make output AML file name uniform. Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13volteer: Create elemi variantWisley Chen
Create the elemi variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:170604353 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELEMI Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-13mb/google/zork: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/asrock/h110m/romstage.c: Drop invalid SPD addressesAngel Pons
Pictures on the internet show that the Asrock H110M-DVS (Kconfig.name) only has two DIMM slots. Since the vendor's website advertises support for dual channel memory, drop the SPD addresses for the second slot of each channel. The result is the same as several other two-slot boards. Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/asrock/h110m/romstage.c: Correct FSP-M UPDsAngel Pons
The DQ and DQS byte maps do not apply to DDR4 configurations, and the RCOMP resistor and target values are not correct for SKL-S (or KBL-S). Drop the byte maps and use RCOMP values for the correct platform type. RCOMP resistor values for all non-socketed platforms are listed in the Platform Design Guide, and also appear in schematics. For SKL-S, the RCOMP resistors are on the CPU and their values have been confirmed by measuring them on an i5-6400, and match the PDG values for SKL-H. RCOMP target values can be guessed from Intel Document #573387 and some of them are also present in datasheet volume 1, under DC specifications. Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb/ocp/deltalake: Update SMBIOS type 9 informationJingle Hsu
Update Slot Designation strings and add SSD0_M2_Boot_Drive for config A. TEST="dmidecode -t 9" to verify the results are expected. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/46125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13mb/google/puff/var/dooly: Update devicetree for audio and display configurationTony Huang
1. Add speaker amplifier ALC1015 2. Enable dmic+ssp registers for speaker and camera DMIC 3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree to remove unused devicesTony Huang
Remove unused device in Dooly no SD card reader no built-in LAN BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/google/puff/var/dooly: Update devicetree for USB configurationTony Huang
Dooly has USBA*2 and USBC*2 BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/google/puff/var/dooly: Update GPIO table for project changeTony Huang
Override unused device SD card reader, built-in LAN ALC1015 speaker amplifier SPK_AMP_ON Update touchscreen/lvds gpio pin BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I6f4d0bf9adc1cce4942a16675a072ffea00bd2e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-13mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revision from ↵Elyes HAOUAS
0x5 to 0x2 DSDT revision 2 is used for ACPI v2 and greater. Change-Id: Ia019358be6574db1b2b06a8a7d52ae996cf45571 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb/intel/latest mainboards: Get rid of power button device in corebootSubrata Banik
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button device in coreboot) This change gets rid of the generic hardware power button from all intel mainboards and relies completely on the fixed hardware power button. Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12mb/clevo/l140cu: clean up memcfgMichael Niewöhner
The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/clevo/l140cu: drop disabled SPD indicesMichael Niewöhner
Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-12mb/clevo/l140cu: drop USE_LEGACY_8254_TIMERMichael Niewöhner
Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream five years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=d43a5ee65143f384357fbfdcace4258e3537c214 Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45960 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/clevo/l140cu: set PS/2 timeout for SeaBIOSMichael Niewöhner
The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45959 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/volteer/var/voxel: disable DdiPortHpdSheng-Liang Pan
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/dedede: refactor DPTF section for simpler overridesSumeet R Pawnikar
Refactor DPTF section of code under the baseboard devicetree and overridetree. This makes override mechanism more simpler, because not all the DPTF fields need to be overridden. BUG=None BRANCH=None TEST=Built and tested on dedede system Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12mb/ibase/mb899/acpi: Convert platform.asl to ASL 2.0 syntaxElyes HAOUAS
It builds same binary for ibase/mb899 using BUILD_TIMELESS=1 Change-Id: I947c4228641abc38a5cd75e51fa2f096fda95d6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45280 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/intel/d945gclf/acpi: Convert platform.asl to ASL 2.0 syntaxElyes HAOUAS
It builds same binary for intel/d945gclf using BUILD_TIMELESS=1 Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45281 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/getac/p470/acpi: Convert 'gpe.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9f5a89946888be3ed033c2ee079f171a23404e90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12mb/getac/p470/acpi/battery.asl: Remove unused remainderElyes HAOUAS
Change-Id: I6ddc3d0c50c5907e24644cea5979d064bea4acd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12mb/intel: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated buils/dsdt.dsl for intel/kblrvp11 are same. Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-10-12mb/facebook: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I91f65fecdcdf41dc41f136e8d66bbf730343aef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46078 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/pcengines/apu2: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie2b1b27c0715fc223e644c3df6c0e9cb876322c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-12mb/pcengines/apu1: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I15b332033f3d492f9e01bb5f1eb25892dee418de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-12mb/google/asurada: Add USB supportCK Hu
Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Signed-off-by: CK Hu <ck.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-12mb/google/dedede: Enable SaGv supportAamir Bohra
Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/volteer: Fix typo in baseboard power limits Sumeet R Pawnikar
Fix typo for power limit values under comment section in baseboard BUG=None BRANCH=None TEST=Build for volteer system Change-Id: I879b9587e863360bf4efda4099d96b42b904377e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12mb/ocp/deltalake: Select correct uart for consolePatrick Rudolph
Tested on OCP deltalake. The console now shows up on the serial. Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-12mb/intel/tglrvp: Enable early EC syncAnil Kumar
- This change is required to execute EC sync in coreboot instead of depthcharge Bug=none Test=build and boot coreboot on TGLRVP Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44689 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/intel/tglrvp: Add support of TPM over SPIShaunak Saha
Bug=none Test=emerge build and boot on tglrvp and check that tpm is probed successfully from coreboot. Cq-Depend:chromium-review:1881839 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-10-12mb/google/dedede: update devicetree for Botenalec.wang
Add trackpad, touchscreen, and usb port to devicetree BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-12mb/google/volteer/variants/eldrid: Add SPD for H5ANAG6NCJR-XNCNick Vaccaro
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H5ANAG6NCJR-XNC DDR4 memory parts. BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12mb/google/zork/dirinboz: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot dirinboz, run integrity test, b:169940185 BRANCH=zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45934 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/zork/dalboz: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP BRANCH=zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1191d73a2a3f72f99de187a946162460acbb287a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45935 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/zork/woomax: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=WIP BRANCH=zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I2fcbe35103020c3444902c077b4985f87f970671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45936 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/zork/vilboz: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot on Vilboz with emmc BRANCH=zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45933 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/jecht: Disable PCIe AERMatt DeVillier
Ethernet hardware on jecht variants doesn't support AER, so disable it to mitigate continuous AER timeout errors in dmesg: > pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0 > pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) > pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000 > pcieport 0000:00:1c.0: AER: [12] Timeout Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/beltino: Disable PCIe AERMatt DeVillier
Ethernet hardware on beltino variants doesn't support AER, so disable it to mitigate continuous AER timeout errors in dmesg: > pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0 > pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) > pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000 > pcieport 0000:00:1c.0: AER: [12] Timeout Change-Id: I0f592a21d08e79cda251e80cd1f1184c4311e9df Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46136 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/puff: Enable SATA0 on wyvernSam McNally
A SATA drive may be connected to SATA0. BUG=b:162909831 BRANCH=puff TEST=none Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-11mb/intel/adlrvp: Add ADL-P romstage mainboard codeSubrata Banik
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD TEST=Able to build and boot ADL-P RVP till ramstage early Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 11:31:37 +0000