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2024-06-12mb/google/volteer/var/drobit: Update boot resolution in VBTMatt DeVillier
Enable the fixed boot mode option in the VBT and set it to 1920x1080, so that drobit boards equipped with 4K screens are legible at boot. TEST=build/boot drobit w/4K screen using edk2 payload, verify boot resolution set to 1080p and UEFI menus readable without a magnifying glass. Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-12mb/google/brox: Generate RAM IDsKun Liu
Generate RAM IDs for K3KL6L60GM-MGCT H9JCNNNBK3MLYR-N6E K3KL8L80DM-MGCU MT62F1G32D2DS-023 WT:C H58G56BK8BX068 BUG=b:333494257 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-12mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. GSPI0_CS0_L -> NF7 GSPI0_MISO -> NF7 GSPI0_MISO -> NF7 GPP_F18 -> EDGE_SINGLE BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-06-12mb/google/nissa/var/pujjoga: Add WWAN power off sequenceLeo Chou
Pujjoga support EM060 WWAN, use wwan_power.asl to handle the power off sequence. BUG=b:346479638 TEST=Build and boot on pujjoga Change-Id: I1273d09385c661835d741691b3c4af26e72a9f86 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83042 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/nissa/var/pujjoga: Tune SX9324 registers settingLeo Chou
Currently, the P sensor does not work. So add SX9324 registers settings based on tuning value from SEMTECH. BUG=b:340749850 TEST=Check i2c register settings on Pujjoga and confirm P sensor function can work by kernel 6.6 driver. Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82689 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-12mb/google/nissa/var/sundance: Add wifi sar tableLeo Chou
Add AX211 wifi sar table for sundance wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 BUG=b:332978681 Test=emerge-nissa coreboot Change-Id: Ide84996da567e4f866a2a1309a6976ed8df635a6 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83044 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/nissa/var/sundance: Add FW_CONFIG probe for WWAN devicesLeo Chou
Add FW_CONFIG probe based on sundance boxster of below devices: WWAN Schematic version: NEC_SHIKIBU_ADL_N_MB_EVT_20240330 BUG=b:332978681 TEST=Boot to OS and verify the WWAN devices is set based on fw_config. Change-Id: I14339201d8ee21c85fefa96a49323e0c25cb8eca Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83041 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/trulo/var/orisa: Disable storage devices based on fw_configAmanda Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1e5e49c1baa8d2b00134c26cc3b69aa15712b512 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Enable HDA Codec ALC256Amanda Huang
We use ALC256 as HDA codec on orisa. Add verb table and the related device tree changes for HDA related registers. BUG=b:338523452 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Add overridetreeAmanda Huang
Add override devicetree based on schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-11mb/razer/blade_stealth_kbl/h3q: add VBIOS tableReagan Bohan
This commit adds the VBIOS table, extracted from Linux sysfs running on the stock firmware version 8.02, to the coreboot tree, required for some graphics backends. Change-Id: I0d1c9795741e112154bfe6885eea744538373d5a Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82460 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-11mb/razer/blade_stealth_kbl: add panel_cfgReagan Bohan
This commit defines the panel_cfg register for the Razer Blade Stealth (Kaby Lake). This enables libgfxinit support. These values are derived from the stock firmware. First, VBIOSes were extracted from the stock firmware. Then, intelvbtool was used to extract the VBT from each of the VBIOS tables. Finally, intel_vbt_decode from igt-gpu-tools was used to extract the register values. Although there were multiple VBIOSes present in the firmware, all VBIOSes across both firmwares (on version 1.50 for the H2U and 8.02 for the H3Q) had the same register values. Change-Id: I4c8b26ffb7a70d08655986084a714206d9d0c96a Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82458 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-11tree: Drop non-existent directories from subdirs-yElyes Haouas
Change-Id: Icb9e72edf3a982a095dceee4da19f90c53fcddd0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-11mb/google/trulo/var/orisa: Add memory configAmanda Huang
Fill in memory config based on the the schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1456f7385e092b606fc0a35b25f3454600af8b23 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82662 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10mb/google/nissa/var/riven: Add GPIO tableDavid Wu
Refer to the reference board of nivviks, and update GPIO settings based on latest schematic (Riven(ZDK)_MB_Proto_0601.pdf). BUG=b:337169542 TEST=Local build successfully. Change-Id: Ic43c743fcc2ec89b5a9e2fbe1a87b833d59f1e74 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82973 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09mb/asrock/h110m/Makefile.mk: Remove superfluous spd from subdirs-yNicholas Chin
The H110M does not use memory down, and the spd directory doesn't exist in the board's directory in the first place. This was probably just copy and paste leftover from some existing Skylake board in the initial port. TEST=Timeless build does not change. Change-Id: I35744310b2bf8a14165dae9808c982e6dc274a74 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83010 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mainboard/emulation/qemu-sbsa: Add qemu-sbsa boardDavid Milosevic
Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). The qemu-sbsa coreboot port runs on EL2 and is the payload of the EL3 firmware (Arm Trusted Firmware). Note that, coreboot expects a pointer to the FDT in x0. Make sure to configure TF-A to handoff the FDT pointer. Example qemu commandline: qemu-system-aarch64 -nographic -m 2048 -M sbsa-ref \ -pflash <path/to/TFA.fd> \ -pflash <path/to/coreboot.rom> The Documentation can be found here: Documentation/mainboard/emulation/qemu-sbsa.md Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-08mainboard: add Dell Latitude E7240Iru Cai
Based on autoport output. It boots to Arch Linux (Linux 6.6.3) from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-08mb/dell: Add Latitude E6430 (Ivy Bridge)Nicholas Chin
Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was not tested. This is based on the autoport output with some manual fixes. The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt` while running version A24 (latest version) of the vendor firmware. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) with the CH347 - Keyboard - Touchpad/trackpoint - ExpressCard (tested with USB 3.0 card) - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch: this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting: needs ACPI code for the EC - Brightness hotkeys: probably EC related - The system reports that the power button was pressed and shuts down when the CPU hits around 86 degrees Celsius, before the CPU can thermal throttle. Likely EC and possibly PECI related. - Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB initializes the 8042 PS/2 controller in a way that is incompatible with how the EC firmware emulates it. GRUB tries to initialize the controller with scan code set 2 without translation, but the EC only ever returns set 1 scan codes to the system and thus is only works as an untranslated set 1 keyboard or a translated set 2 keyboard, regardless of commands to set the scan code. A USB keyboard works fine. Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77444 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08tree: Remove unused <option.h>Elyes Haouas
Change-Id: Ia3df14ebd365c00902b5d2ba300d8ade4c2d6c26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-08mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/asus/p8z77-m: Update USB current map to match vendorKeith Hui
This board has used the USB current map from asus/p8z77-m_pro since it first landed in coreboot, which actually doesn't match vendor firmware. Apply values obtained from hardware while running vendor firmware to both native and MRC config. Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82756 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Add consolidated USB port config for SNB+MRC boardsKeith Hui
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/asus/p8z77-v: Apply updated USB current map to sb devicetreeKeith Hui
This map is found stored in plain text in vendor firmware image. They will take effect when USB config is transitioned to southbridge devicetree. Change-Id: Iab0a225560856771407bb815ff4d8bc95d0f884f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-07mb/*: Copy bd82x6x boards' USB port config into devicetreeKeith Hui
For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/google/brya/var/xol: add support for wifi sar tableYH Lin
Add wifi sar table support for xol. Bit 31 in CBI/FW_CONFIG is used to select different sar table (index 0 or 1) but only 0 is in used at the moment. BUG=b:344274789 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Id4dc74c4f2a807d2e531b419ecb7b590d4c32ac2 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/google/brox/var/brox: update thermal settings to start fan earlySumeet Pawnikar
Current existing temperature thresholds of TSR1 sensor are set at 60C to start fan. Due to this CPU gets hot and temperature goes over 80C. In this situation, fan does not even start to lower down CPU temperature. With updated new settings based on tuning from thermal team, start fan early at 40C for TSR0 and TSR1 so the CPU temperature stays below 80C. BUG=b:339493551 TEST=Built and tested on google/brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I4765c13c10e436733d8c9d017085968daa561ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82784 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-07mb/siemens/mc_apl1: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: If43089560a391d6a844ef1716b277e3146c66945 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-06-07mb/google/rex0: Restore SSD power sequencing GPIOs in ramstageSubrata Banik
This change restores the EN_PP3300_SSD GPIO configuration in the ramstage for the Rex0 variant. This is necessary to enable testing of RO lockdown scenarios on FSI'ed Screbo devices, where bootblock changes are not applicable. Additionally, ensures locking the GPIO PAD from getting misconfigured after booting to OS. BUG=b/337971452 BRANCH=firmware-rex-15709.B TEST=Able to boot google/rex with RO locked to an older version without SSD GPIO refactored, and RW is with the latest revision. Change-Id: Ia7564b14a20d00e9bb2c9466b7a737dd97f01351 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-07mb/google/nissa/var/pujjoga: Add wifi sar tableLeo Chou
Add AX211 and AX203 wifi sar table for pujjoga wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 WIFI_SAR_TABLE_AX203: 1 BUG=b:336167281 Test=emerge-nissa coreboot Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-06-07mb/google/nissa/var/pujjoga: Add FW_CONFIG probe for WWAN devicesLeo Chou
Add FW_CONFIG probe based on pujjoga boxster of below devices: WWAN Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:336167281 TEST=Boot to OS and verify the WWAN devices is set based on fw_config. Change-Id: I94cb9ffe47888a8b7b5c6837ddfc390a1d2e77d1 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-07mb/google/dedede/var/boten: Add new supported memory partLeo Chou
Add bookem new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Zilia SDVB8D8A34XGCL3N3T BUG=b:344482259 TEST=Use part_id_gen to generate related settings Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82783 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/google/brask/var/bujia: fix type-c USB2 problemShon Wang
Enable type-c port 0 USB2 function. BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I0d7adc329a8c26941957d7a7472a5166b07bda5b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82903 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/*: Add Kconfig values for battery informationSean Rhodes
Add Kconfig strings for the battery: * Model * OEM * Technology Change-Id: Ibbce87ad54874f490af45c41f31956a7e9e996f3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81401 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/labtop/cml: Increase TCC OffsetSean Rhodes
These values were configured based on a default value of 110, but for CML, it's actually 100. Adjust it accordingly. Change-Id: Ibffeeab67a7277625db9bdedca36d759ff0e72f6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81414 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/starbook/kbl: Configure the TCC Offset based on Power ProfileSean Rhodes
Configure the TCC Offset based on the active power profile Change-Id: I58940441a7cefc7a2a07e5e9f7e8a15cb8730ef3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-07mb/starlabs/starbook/kbl: Use function for getting power profileSean Rhodes
All other variants use a function and definitions to get the power profile. Make this board to the same. Change-Id: I07ce71e20bd71229bb0cd3438ab59140cd0d8b42 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81412 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/starbook/cml: Switch to the merlin ECSean Rhodes
Change-Id: I27062c38c10df1d03f563b2f5391f79a3b6ee4fe Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81411 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07soc/intel/common/uart: Drop chip in favor of devicetree opsArthur Heymans
It is now possible to hook up device ops directly to devices in devicetree which removes the need for a fake chip. This also fixes Hermes booting as the PCI ops were incorrectly hooked up to a dummy device. The intel uart driver was requesting a resource from the generic device and died since it does not exist: [EMERG] GENERIC: 0.0 missing resource: 10 This was broken in commit b9165199c32a (mb/prodrive/hermes: Rework UART devicetree entry). Change-Id: I3b32d1cc52afaed2a321eea5815f2957fe730f79 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82940 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-07mb/cwwk/adl: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The CWWK CW-ADL-4L-V1.0 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the CWWK CW-ADL-4L-V1.0 board. Change-Id: Ie3844cb24740e4d95ee835a44e55b4d5cb6854e5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07mb/aoostar/wtr_r1: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The aoostar/wtr_r1 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the aoostar/wtr_r1 board. Change-Id: I68feeaaffd825013ae1012694047b067535e7341 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82914 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/siemens/chili: Remove superfluous device entries from dtFelix Singer
Remove the entries which have the same state as the ones from the chipset devicetree. Change-Id: I4981cd835ef28a673d480808dd486fed4d9b45e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-06mb/google/brox/var/lotso: Add dq map settingJian Tong
Based on lotso EVT schematics add dq map settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
2024-06-06mb/asrock: Add Z87E-ITX (Haswell)Nicholas Chin
This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. The VBT was copied from /sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware. The flash chip is 8MiB in a socketed DIP8 package, making it easy to externally flash to recover from a brick. Working: - Haswell MRC.bin - S3 suspend and resume - Libgfxinit - HDMI - DVI-I (including passive DVI to VGA adapter) - DisplayPort - SATA ports - mSATA SSD - mPCIe WiFi slot - Rear USB ports - USB 3.0 header - Audio header - Ethernet - x16 PCIe slot - EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector) - edk2 (MrChromebox uefipayload_202309) Not Tested: - PS/2 keyboard/mouse - eSATA - USB 2.0 header Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/intel/coffeelake_rvp: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I98aa3f582963f76690f907b678ac322ed4cc99d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82846 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/starlabs/starbook: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I972516443bc57e193aefd54516ca994087d92054 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-05mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-06-05mb/ibm/sbp1: Update PCIe port slot number for NICNaresh Solanki
Based on schematic, update slot number for PCIe port used for NIC controller. Change-Id: I7a1ead8f7e4588db45303041e60dbfe27ee12ea7 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-05Xeon-SP boards: Factor out OCP VPD `get_cxl_mode()` implAngel Pons
There's two copies of the `get_cxl_mode()` function to map the OCP VPD value to the values expected by platform code. As this is unnecessary, have a single copy of this function in the OCP VPD driver code. As the `get_cxl_mode()` function is Xeon-SP only, keep it in a separate file. This change simplifies things for boards using OCP VPD for CXL and has no impact for boards *not* using OCP VPD: - Boards not using OCP VPD can still define get_cxl_mode() in mainboard code as needed, just like they were able to do before. - Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not enabled), this code won't get compiled in at all (see `Makefile.mk`). - Boards using OCP VPD and CXL will automatically make use of this `get_cxl_mode()` definition, which should be the same for all boards. It is possible that this may need to be expanded/adapted in the future, which is easy to handle in a follow-up commit when the need arises. TEST=Build and boot on intel/archercity CRB Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-05mb/google/trulo/var/orisa: Configure TPM IRQ for orisaAmanda Huang
Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04mb/starlabs/lite: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-04mb/google/brya/var/xol: Enable FSP UPD LpDdrDqDqsReTrainingSeunghwan Kim
Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen issue. Reference: https://review.coreboot.org/c/coreboot/+/79527 > FSP default value for LpDdrDqDqsReTraining is 1. For boards > that didn't set LpDdrDqDqsReTraining to any value, 0 was being > assigned and it caused black screen issue. BUG=b:332980211 BRANCH=brya TEST=Built and verified there is no black screen issue during power on/off test for over 100 cycles. Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-04mb/google/brask/var/bujia: change ALC5650 to ALC5682I-VSShon Wang
Due to system spec change, change audio codec ALC5650 to ALC5682I-VS BUG=b:329787697 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-03mb/razer/blade_stealth_kbl: Add H3Q variantReagan Bohan
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally committed, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. 5. The gpio is different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03mb/system76/rpl: Fix addw4 Kconfig nameTim Crawford
Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03mb/system76/rpl: Hook up TAS5825M initTim Crawford
Ensure per-board smart amp init is configured. Fixes speaker output on oryp12. Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Fixes: 8b9716e2269d ("mb/system76/rpl: Add Oryx Pro 12 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-06-03mb/system76: Add SPDX ID to devicetree filesTim Crawford
Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-31mainboard/google/rex: Enable Rex64 build configurationSubrata Banik
- Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31mb/google/brya/var/nova: Update USB ports settingKenneth Chan
Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-05-31mb/google/trulo: Support OCP fault on A0/1 portsPranava Y N
The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30tree: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30mb/siemens/mc_ehl5: Remove DDI settings from devicetreeMario Scheithauer
Since this mainboard no longer uses the FSP GOP driver, the DDI port settings are no longer necessary. The GOP driver was used in the initial phase of development where we used Tianocore as payload for some test cases. Finally, this mainboard uses a self-made Linux payload, which does the graphic initialization. BUG=none TEST=Boot into Linux and check if graphic works correctly Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82663 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: Add Adder WS 4 as a variantTim Crawford
The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - All USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29mb/system76/rpl: Add Oryx Pro 12 as a variantTim Crawford
The Oryx Pro 12 (oryp12) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I11cf2dbd1512ebae44e0109bdb78e6eafa027444 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: darp9: Add SSD RTD3 configsTim Crawford
Some drives block the CPU from reaching C10 during S0ix suspend without the RTD3 configs. Fixes suspend with the following drives: - Kingston KC3000 (SKC3000D/4096G) - Kingston HyperX (SHPM2280P2H/240G) - Solidigm P44 Pro (SSDPFKKW010X7) The following drives continue to work: - Samsung 970 Evo (MZVLB250HAHQ) - WD Black SN770 (WDS250G3X0E) - WD Green SN350 (WDS240G2G0C-00AJM0) - WD Blue SN570 (WDS100T3B0C) Change-Id: Ia369727d0f1aa5ff546cfb5700a63063730e8248 Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-05-29mb/intel/mtlrvp: Enable EC MKBP deviceJay Patel
MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:342227155 TEST=Able to build coreboot for mtlrvp platform and switch tablet mode. Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Signed-off-by: Jay Patel <jay2.patel@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82612 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-05-29mb/google/nissa/var/sundance: Add WWAN power off sequenceLeo Chou
Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/pujjoga: Update touchscreen IC settingsRoger Wang
Modify the Goodix touchscreen from new vendor and remove 3 unused touchscreens. According to the information provided by the key-part team. BUG=b:340689681 TEST=Build and check Goodix touchscreen can work. Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/sundance: Update eMMC DLL settingsRoger Wang
Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-28mb/system76/tgl: Update VBTs to version 250Tim Crawford
Commit 4c7e97b26a34 ("Update fsp submodule to upstream master branch") included an update to the VBT from 240 to 250, breaking parsing of existing VBTs. After that commit, the VBT was parsed as (from gaze16-3060-b): [DEBUG] PCI: 00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000 [DEBUG] PCI: 00:02.0 init finished in 6 msecs When the expected output is: [DEBUG] PCI: 00:00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000 [DEBUG] PCI: 00:00:02.0 init finished in 6 msecs Generate blobs for the new version using Intel Display Configuration Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs. (For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.) Tested on all affected systems: - darp7 - galp5 - gaze16-3050 - gaze16-3060 - gaze16-3060-b - lemp10 - oryp8 Tested: - Boot splash displays on screen again - Firmware setup menu is rendered, at correct resolution Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Tested-by: Jacob Kauffmann <jacob@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-28mb/google/brox: Add romstage early graphicsSowmya Aralguppe
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [SPEW ] bootmode is set to: 0 (boot with full config) [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. [DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes) [WARN ] CBFS: 'preram_locales' not found. [ERROR] ux_locales_get_text: preram_locales not found. [DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes) [INFO ] ELOG: NV offset 0xf20000 size 0x4000  elogtool list: 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-28mb/google/trulo: Add initial devicetree.cbSubrata Banik
This patch adds initial PCI device entries into the baseboard devicetree.cb. TEST=Able to build google/trulo. Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Trulo variants to override the USB ports as per the target board design. TEST=Able to build google/trulo. Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Program EC ranges (host cmd and memory map)Subrata Banik
This patch adds chip config entries for EC host cmd and memory map ranges. TEST=Able to build Google/Trulo. Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)Federico Amedeo Izzo
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200 SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - DDR4 RAM (tested with Crucial 16GB 3200MHz CL22) - Automatic FAN control (IT8613E Super I/O) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the Super I/O registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Patchset 13: Change Super I/O Fan configuration to reduce fan noise Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set PsysPL2 value to 178WTony Huang
Adjust setting as recommended by power team. Add ramstage.c in Makefile.inc to set psys_pl2_watts in variant_devtree_update(). Also copy CPU power limit values from ovis baseboard. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting [INFO] CPU PsysPL2 = 178 Watts [INFO] Overriding PsysPL2 (178) [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-27mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 WTony Huang
Adjust settings as recommended by thermal team. Set PL1 max value tdp_pl1_override from 28W to 33W. PL2, PL4 remain the same as CPU default. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set TCC_offset to 5Tony Huang
Adjust settings as recommended by thermal team. Set tcc_offset value to 5 in devicetree. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27mb/google/rex/var/deku: Update DPTF parametersTony Huang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:308704811#comment4. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-24soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.hShuo Liu
get_cxl_mode() is the interface for CXL mode config check used by SoC codes. It could be implemented by mechanisms outside of the SoC codes, e.g. board codes or OCP VPD driver. Move the interface declaration out of soc/util.h to a dedicated header, a.k.a., soc/config.h, so that the implementation codes do not need to include soc/util.h where there are lots of irrelevant definitions. Future SoC config check interfaces could be added to soc/config.h as well. The default weak implementation is moved out of util.c to config.c as well. TEST=Build and boot on intel/archercity CRB Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24mb/google/trulo: Refactor gpio pad configurationSubrata Banik
This patch tries to simplify the baseboard/variant GPIO programming for Google/Trulo. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant) TEST=Able to build google/orisa. Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-24mb/google/nissa: Fix potential null pointer dereferenceSubrata Banik
* Introduce a null check before calling `gpio_padbased_override` in `variant_configure_pads`. * This prevents potential errors in cases where the `variant_gpio_override_table` function returns a null pointer, indicating that there are no override pads to configure. BUG=b:334826281 TEST=Able to avoid hang incase there is no GPIO override. Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23device: drop unnecessary CHECK_REV_IN_OPROM_NAME optionFelix Held
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6de533c536044698d85404427719b8f534870fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/google/brox/var/brox: Remove mux references from typec portPrashant Malani
The Type-C kernel driver no longer programs the AP mux, as of https://review.coreboot.org/c/coreboot/+/82077. So remove device references to the TCSS Mux control device from the Type-C port driver. This eliminates the following kernel error which was observed as a result of the kernel trying to program muxes it no longer has control over: [ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95 [ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95 BUG=b:341331428 TEST=Run system reboot; configure mux kernel errors no longer seen. Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/amd/birman/display_card_type.h: add missing includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5208ceeec17051e7849263a4caa0838efd59c044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23mb/amd/birman/display_card_type.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/google/brya: Add romstage early graphics for nissaRonak Kanabar
1) Add all changes needed for early graphics 2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa The InnoLux (N156HCN-EBA C7) panel is used for the device tree. BUG=b:296433986 TEST=On-screen text message seen during MRC training on Craask Logs: [NOTE ] MRC: no data in 'RW_MRC_CACHE' [SPEW ] bootmode is set to: 0 [0.171409] DP PHY mode status not complete [0.175509] DP PHY mode status not complete [0.179799] DP PHY mode status not complete [0.184087] DP PHY mode status not complete [0.188376] DP PHY mode status not complete [0.192665] DP PHY mode status not complete [0.196954] DP PHY mode status not complete [0.201243] DP PHY mode status not complete [0.205532] DP PHY mode status not complete [0.209821] DP PHY mode status not complete [0.214110] DP PHY mode status not complete [0.218397] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/cwwk: Add CWWK CW-ADL-4L-V1.0 boardBrandon Weeks
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE ports, similar boards are available in other port configurations. As a low cost, relatively high performance board with 4 NICs, it is well suited for networking or 'homelab' tasks. CPU: Intel N100 or N350 Memory: DDR5-4800 SODIMM (max 16 GB) NIC: 4x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 4x Ethernet - Display Port - HDMI - 4x USB 2.0 - Micro SD Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot - ACPI S3 Not working / not tested: - Fan (ITE IT8613E) - Audio - S0ix - Internal USB ports VBT extracted from vendor UEFI firmware version ADLN 0.01 x64 (04/04/2023 11:42:38). Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-23mb/google/nissa/var/orisa: Generate RAM ID for Micron MT62F512M32D2DR-031 WT:BAmanda Huang
Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) BUG=b:337178014 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22Revert "mb/google/rex/var/deku: Configure GPIO"Tony Huang
This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb. Reason for revert: Intel suggest is NC only. No need to change anything that isn't broken. Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/prodrive/hermes: Tidy up hda_verb.cAngel Pons
Use the `AZALIA_PIN_CFG_NC(0)` macro instead of `0x411111f0` and tidy up some comments (align them and be consistent with capitalisation). Tested with BUILD_TIMELESS=1, prodrive/hermes remains identical. Change-Id: I1ff1197b1309fc0e5b978d6d36867a3f1a68c67c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add USB PHY configFelix Held
Now that we also have the devicetree registers for the USB PHY config in the openSIL case, add the USB PHY config setting from the Phoenix with FSP devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a0acbf1b9d705dbf09f4480eb35e71e587ddd44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 configFelix Held
Use the now common get_ddi1_type function to update the connector type of the DDI1 port to match the display output extension card plugged into the reference board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman: factor out get_ddi1_typeFelix Held
Both port descriptor files used in the FSP case contain an identical get_ddi1_type implementation, so factor it out into a separate file. This will also allow using the same function in the openSIL case in a following patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add static DDI configurationFelix Held
Add a static DDI port configuration to the devicetree used in the Phoenix with openSIL case. The configuration is taken from the birman_ddi_descriptors array in port_descriptor_phoenix.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'Felix Held
Remove the unexpected '<' char at the end of the comment about the PSPP policy config. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 17:22:14 +0000