diff options
| author | Pranava Y N <pranavayn@google.com> | 2024-05-24 14:20:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-05-31 09:13:17 +0000 |
| commit | 3303b3684b9a8e5b5863a5e4bf4641029fe65a2c (patch) | |
| tree | b1a6365332827b8722a7ca4b1bd8ba1fbf676013 /src/mainboard | |
| parent | 11fad8fc86a902347365491c4239e45531a392e6 (diff) | |
mb/google/trulo: Support OCP fault on A0/1 ports
The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.
BUG=b:335858378
TEST= Able to build google/trulo
Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/gpio.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/overridetree.cb | 8 |
2 files changed, 10 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index beee6fcb29..1a6d1b1466 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -8,7 +8,10 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* TODO */ + /* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG), + /* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index ee861420f6..9285c33043 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/alderlake - device domain 0 on - end + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + + device domain 0 on + end end |